Switched substrate bias for MOS-DRAM circuits

A MOS-DRAM comprising:

• a plurality of memory cells arranged in rows and columns;
• a logic circuit used for row operating and column operating circuits, said logic circuit including at least one MOS-FET to which a first potential or a second potential is supplied as a substrate potential;
• a voltage supply means for supplying said first and second potentials;
• and
• means for providing one of said first potential and said second potential to said at least one MOS-FET of said logic circuit as said substrate potential according to an operation state of said MOS-DRAM array, wherein
• said means for providing one of said first potential and said second potential includes
• a level shift circuit receiving a signal representative of said operation state of said MOS-DRAM array and outputting a control signal in accordance with said operation state of said MOS-DRAM, and
• a switch circuit receiving the control signal output from the level shift circuit to control switching between said first potential and said second potential to supply either the first potential or second potential as said substrate potential to the MOS-FET of each memory cell as said substrate potential.

A MOS-DRAM comprising:

• a plurality of memory cells arranged in rows and columns, each memory cell including an MOS-FET to which a first potential or a second potential is supplied as a substrate potential;
• a voltage supply means for supplying said first and second potentials;
• and
• means for providing one of said first potential and said second potential to the MOS-FET of each memory cell as said substrate potential according to a signal for activating said plurality of memory cells, wherein
• said means for providing one of said first potential and said second potential includes
• a level shift circuit receiving a signal representative of said operation state of said MOS-DRAM array and outputting a control signal in accordance with said signal for activating said plurality of memory cells, and
• a switch circuit receiving the control signal output from the level shift circuit to control switching between said first potential and said second potential to supply either the first potential or second potential as said substrate potential to the MOS-FET of each memory cell as said substrate potential.