Drive circuit and method for controlling the cross point levels of a differential CMOS switch drive signal

A method of driving a differential CMOS switch, said switch including a pair of differentially connected PMOS transistors, each transistor having a gate, a drain, and a source, said sources being connected at a reference node and together receiving a signal current, comprising:

• applying a pair of complementary digital signals to the PMOS transistors' gates, respectively, said complementary digital signals switching between low and high voltage levels at a first duty cycle of substantially 50% causing said transistors to turn fully on and fully off, respectively, so that substantially all of the signal current flows, through the transistor that is fully on to switch a differential output signal between the transistors' respective drains at a second duty cycle of substantially 50% and to produce a switched voltage level at said reference node which is offset from the low voltage level at the gate of the fully on transistor by that transistor's fully on gate-to-source voltage, the complementary digital signals' voltage levels intersecting at a pair of cross points when switching between the low and high voltage levels so that said signal current is apportioned equally between the pair of transistors and their cross point gate-to-source voltages are reduced from their fully on gate-to-source voltages;
• and
• reducing the complementary digital signals' first duty cycle below 50% to reduce the cross point voltage levels to compensate for the reduction in the transistors' cross point gate-to-source voltage so that the voltage level at the reference node is maintained at approximately the switched voltage.

A differential drive circuit that receives, a pair of complementary digital input signals that switch at a first duty cycle and together define a differential input drive signal and shapes them to produce a pair of complementary shaped signals that switch between high and low voltage levels at a second duty cycle and together define a differential shaped drive signal for driving a differential CMOS switch, said differential CMOS switch including a pair of CMOS output transistors having respective gates, drains and sources, said sources being connected at a reference node to receive a first signal current, said differential CMOS switch responding to the application of the differential drive signal at its gates by producing a differential output signal between said drains and producing a switched voltage level at said reference node when the transistors are fully switched, the differential drive circuit comprising:

• a reference terminal for receiving a reference voltage;
• a pair of diode connected PMOS load transistors having gate-drain junctions that are connected to said reference terminal and having sources that are electrically coupled to the output transistors' gates to apply high voltage levels thereto;
• a pair of NMOS load transistors having gates that receive the respective complementary digital input signals, sources that are connected to said reference terminal, and drains that are connected to the output transistors' gates, said NMOS load transistors turning fully on in response to the digital input signals' high voltage levels to apply low voltage levels to the output transistors' gates;
• a current source that supplies a second signal current;
• and
• a pair of single-ended CMOS switches that are connected to the output transistors' gates and the PMOS load transistors and respond to a pair of complementary digital control signals that are derived from said digital input signals, one said single-ended CMOS switch responding to a first control state by directing the second signal current through the PMOS load to switch the shaped signal applied at one of said output transistor's gate to a high voltage level that is offset from the reference voltage by the PMOS load transistors' gate-to-source voltage, and the other said single-ended CMOS switch responding to a second control state by cutting off the second signal current to the respective fully on NMOS load transistor to switch the other shaped signal applied at the other said output transistor's gate to a low voltage level that is substantially equal to the reference voltage, the pair of shaped signals intersecting at a pair of cross points when switching high-to-low and low-to-high, respectively, and together define the differential shaped drive signal;
• said drive circuit's PMOS and NMOS load transistors having channel geometries defined by their gate width and length that together with the amount of said second signal current shift the shaped signals' second duty cycle with respect to the digital input signals' first duty cycle to a) set the voltage levels of the shaped signals at the cross points so that the voltage level at the reference node is maintained at the switched voltage level when the output transistors are at the cross points and to b) maintain the duty cycle of the differential shaped drive signal at approximately the same duty cycle as the differential input drive signal, wherein the connections of the pair of output transistor gates to the load transistors and the single-ended CMOS switches form respective driver output terminals.

A method of driving a differential CMOS switch that includes a pair of CMOS output transistors having respective gates that form a differential input, respective drains that form a differential output, and respective sources that are connected at a reference node and together receive a signal current, comprising:

• receiving a complementary pair of digital input signals that switch between on and off voltage levels at an approximately 50% duty cycle and intersect at a pair of cross points approximately halfway between the on and off voltage levels, said signals together defining a differential drive signal that switches between on and off voltage levels at a substantially 50% duty cycle and has a voltage level of zero at said cross points;
• adjusting the digital input signals' duty cycle away from 50% to move their voltage levels at the cross points away from the halfway voltage level without changing the differential drive signal's 50% duty cycle;
• and
• applying the adjusted digital input signals to the differential input of the differential CMOS switch, said digital input signals' on and off voltage levels causing the switch's output transistors to turn fully on and fully off, respectively, so that substantially all of the signal current flows through the output transistor that is fully on to switch a pair of complementary analog signals at the output transistors' respective drains thereby producing a differential output voltage signal having a 50% duty cycle across the differential CMOS switch's differential output, the flow of substantially all of the signal current through one said output transistor producing a fully switched voltage level at said reference node that is offset from the voltage level at the gate of the fully on output transistor by that transistor's gate-to-source voltage, said differential drive signal's zero voltage level at the cross points causing the signal current to be apportioned equally between the pair of output transistors so that their gate-to-source voltages are reduced,
• said digital input signals' duty cycle being adjusted away from 50% to move their voltage levels at the cross points towards the fully switched voltage level at the reference node to compensate for the reduction in the output transistors' gate-to-source voltages so that the voltage level at the reference node is maintained at approximately the fully switched voltage level thereby reducing the amount of distortion in the CMOS switch's differential output voltage signal.

A precision limited switch, comprising:

• a pair of input terminals for receiving a complementary pair of digital input signals that switch between on and off voltage levels at an approximately 50% duty cycle and, at a pair of cross points, intersect at a first cross point voltage that is approximately halfway between its on and off voltage levels, said pair of digital input signals together defining a differential input drive signal that switches at a substantially 50% duty cycle;
• a drive circuit comprising:
• a reference terminal for receiving a reference voltage;
• a pair of output terminals;
• a pair of diode connected PMOS load transistors having gate-drain junctions that are connected to said reference terminal and having sources that are electrically coupled to the respective output terminals;
• a pair of NMOS load transistors having gates that receive the pair of digital input signals, sources that are connected to said reference terminal, and drains that are connected to the respective output terminals, said NMOS load transistors turning fully on in response to the digital input signals' high voltage levels;
• a current source that supplies a first signal current;
• and
• a pair of single-ended CMOS switches that switch in response to the digital input signals to direct the first signal current to the PMOS load transistor opposite the fully on NMOS load transistor thereby switching a complementary pair of shaped digital signals at the output terminals between high voltage levels that are offset from the reference voltage by the PMOS load transistors' gate-to-source voltages and low voltage levels that are substantially equal to the reference voltage, said shaped signals together defining a differential shaped drive signal;
• and
• a differential CMOS switch that comprises a pair of CMOS output transistors having respective gates that form a differential input for receiving the differential shaped drive signal, drains that form a differential output, and sources, said sources being connected at a reference node to receive a second signal current, said differential shaped drive signal causing the pair of CMOS output transistors to turn fully on and fully off, respectively, so that substantially all of the second signal current flows through the output transistor that is fully on to switch a pair of complementary analog signals at the output transistors' respective drains, which together define a differential output voltage signal across the differential output, the flow of substantially all of the second signal current through one said output transistor producing a fully switched voltage level at said reference node that is offset from the voltage level at the gate of the fully on output transistor by that transistor's gate-to-source voltage, said digital shaped drive voltage signal having a zero voltage level at the cross points that causes the second signal current to be apportioned equally between the pair of output transistors so that their gate-to-source voltages are reduced,
• said PMOS and NMOS load transistors having channel geometries defined by their gate width and length that together with the amount of said first signal current set the shaped digital signals' duty cycle at a non-50% level so that a) the shaped digital signals cross point voltage levels compensate for the reduction in the output transistors' gate-to-source voltages at the cross points so that the voltage level at the reference node is maintained at the switched voltage and b) the duty cycles of the differential shaped drive signal and the differential output voltage signal are approximately 50%.