Master-slave bistable latch with clock input control

A semiconductor integrated circuit, comprising:

• input data inverting means receiving input data for outputting inverted input data which is a logical inversion of said input data;
• first data holding means receiving said input data and said inverted input data, for holding a logical value indicated by said input data as first internal output data and holding a logical value indicated by said inverted input data as first inverted internal output data in synchronization with a controlling clock;
• second data holding means receiving said first internal output data and said first inverted internal output data, for holding a logical value indicated by said first internal output data as second internal output data and holding a logical value indicated by said first inverted internal output data as second inverted internal output data in synchronization with said controlling clock;
• first external data output means for logically inverting said second inverted internal output data to output output data;
• second external data output means for logically inverting said second internal output data to output inverted output data;
• and
• clock control means receiving first to fourth comparison data and a reference clock, for outputting said reference clock or a fixed voltage as said controlling clock on the basis of said first through fourth comparison data;
• said clock control means comprising, a first AND gate receiving said first and second comparison data for executing AND operation of said first comparison data and said second comparison data to output first logical data,
• a second AND gate receiving said third and fourth comparison data for executing AND operation of said third comparison data and said fourth comparison data to output second logical data,
• an OR gate for executing OR operation of said first and second logical data to output third logical data, and
• a clock control gate receiving said reference clock and said third logical data for outputting said reference clock/said fixed voltage as said controlling clock on the basis of "H"/"L" of said third logical data,
• wherein said first comparison data is one data of said input data and said inverted input data,
• when said first comparison data is said input data, said second comparison data is one data of said first inverted internal data, said second inverted internal data and said inverted output data, said third comparison data is data of said inverted input data, and said fourth comparison data is one data of said first internal data, said second internal data and said output data, and
• when said first comparison data is said inverted input data, said second comparison data is one data of said first internal data, said second internal data and said output data, said third comparison data is said input data, and said fourth comparison data is one data of said first inverted internal data, said second inverted internal data, and said inverted output data.

A semiconductor integrated circuit, comprising:

• first to n-th data holding means respectively receiving first to n-th input data, for in synchronization with a common controlling clock, holding logical values indicated by said first to n-th input data respectively as first to n-th output data and holding inverted values of the logical values respectively indicated by said first to n-th input data as first to n-th inverted output data;
• first to n-th comparison means respectively receiving said first to n-th input data and said first to n-th output data, for respectively comparing said first to n-th input data and said first to n-th output data to respectively output first to n-th comparison signals indicating match/mismatch;
• and
• clock control means receiving said first to n-th comparison signals and a reference clock, for outputting a fixed voltage as said controlling clock only when said first to n-th comparison signals all indicate match and otherwise outputting said reference clock as said controlling clock.

A semiconductor integrated circuit, comprising:

• input data selecting means receiving input data and scan input data, for outputting one data of said input data and said scan input data as selection data on the basis of a selection signal;
• data holding means receiving said selection data for holding a logical value indicated by said selection data as output data in synchronization with a controlling clock;
• and
• clock control means receiving said selection data, said output data and a reference clock, for comparing said selection data and said output data to, on the basis of match/mismatch thereof, output a fixed voltage/said reference clock as said controlling clock.