Method and apparatus for test mode entry during power up
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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Abstract
An integrated circuit includes test circuitry and test mode enable circuitry. During power-up, an over-voltage on a package pin of the integrated circuit can initiate a test mode. The test mode enable signal may be latched into its activity state by a signal provided on a second package pin. Thereafter, the first and second package pins may be used in the normal voltage range during the test operations.
Claims28
In an integrated circuit (IC) having operational-circuitry and test-circuitry connected to said operational-circuitry, test-mode-enable circuitry for enabling said test-circuitry to operate during a time-interval of power-up of said IC from a power terminal that is connected to source of IC operating voltage, said power terminal initially having a potential of zero volts applied thereto as said power-up time-interval begins, thereafter having a first low voltage applied thereto, and then having a second higher voltage applied thereto, said test-circuitry being enabled upon receiving a test-mode signal, said test-mode-enable circuitry comprising:
- a first terminal for receiving a first signal generally coincident with said beginning of said power-up time-interval;
- a second terminal for receiving a second signal at a time during said power-up time-interval;
- first-voltage-threshold-sensitive means responsive to an input of a first threshold level;
- said first-voltage-threshold-sensitive means having an output connected to provide said test-mode signal to said test-circuitry, and having an input connected to receive a voltage difference between said first terminal and said power terminal;
- said first-voltage-threshold-sensitive means operating to apply said test-mode signal to said testing-circuitry when said source of operating voltage equals said first low voltage;
- signal-latching means having an input, and having an output operating to apply said test-mode signal to said testing-circuitry;
- second-voltage-threshold-sensitive means;
- said second-voltage-threshold means having an input connected to receive a voltage difference between said second terminal and said power terminal, and having an output connected to said input of said signal-latching means;
- said second-voltage-threshold-sensitive means operating to control said signal-latching means to cause said signal-latching means to apply said test-mode signal to said testing-circuitry upon the occurrence of said second signal, and when said source of operating voltage equals said second higher voltage;
- and
- said test-mode signal being thereafter maintained independent of said first and second signals received respectively by said first and second terminals.
In combination, operational-circuitry, test-circuitry connected to said operational-circuitry, and test-mode-enable circuitry for enabling said test-circuitry, by applying a test-mode signal to said test-circuitry, said test-mode-enable circuitry comprising:
- a voltage source of a first polarity, said voltage source providing an output voltage that is initially zero volts at a beginning of a time-interval, said output voltage progressively increasing during said time-interval, first to a low voltage, and then to a high voltage;
- a power terminal connected to said voltage source;
- a first terminal for receiving a first signal of an opposite polarity generally coincident with said beginning of said time-interval;
- a second terminal for receiving a second signal of said opposite polarity at a time within said time-interval at which said output voltage of said voltage source is generally equal to said high voltage;
- first-voltage-threshold-sensitive means responsive to an input of a first threshold level;
- said first-voltage-threshold-sensitive means having an output connected to provide said test-mode signal to said test-circuitry, and having an input connected to receive a voltage difference between said first terminal and said power terminal;
- said first-voltage-threshold-sensitive means operating to apply said test-mode signal to said testing-circuitry when said output voltage of said voltage source generally equals said low voltage;
- signal-latching means having an input, and having an output operating to apply said test-mode signal to said testing-circuitry;
- second-voltage-threshold-sensitive means;
- said second-voltage-threshold means having an input connected to receive a voltage difference between said second terminal and said power terminal, and having an output connected to said input of said signal-latching means;
- and
- said second-voltage-threshold-sensitive means operating to control said signal-latching means to cause said signal-latching means to apply said test-mode signal to said testing-circuitry upon the occurrence of said second signal.
In an integrated circuit (IC) having operational-circuitry and test-circuitry connected to said operational-circuitry, a method of enabling said test-circuitry to operate during a time-interval of power-up of said IC from a power terminal that is connected to source of operating voltage, said power terminal initially having a potential of zero volts applied thereto as said power-up time-interval begins, thereafter having a first low voltage applied thereto, and then having a second higher voltage applied thereto, said test-circuitry being enabled upon receiving a test-mode signal, said method comprising the steps of:
- providing first terminal means for receiving a first signal at a time generally coincident with said beginning of said power-up time-interval;
- providing second terminal means for receiving a second signal at a later time during said power-up time-interval;
- providing first-voltage-threshold-sensitive means responsive to an input of a first threshold level;
- connecting an output of said first-voltage-threshold-sensitive means to provide said test-mode signal to said test-circuitry;
- connecting an input of said first-voltage-threshold means to receive a voltage difference between said first terminal and said power terminal;
- said first-voltage-threshold-sensitive means operating to apply said test-mode signal to said testing-circuitry when said source of operating voltage has risen to said first low voltage;
- providing signal-latching means having an input, and having an output operating to apply said test-mode signal to said testing-circuitry;
- providing second-voltage-threshold-sensitive means;
- connecting an input of said second-voltage-threshold means to receive a voltage difference between said second terminal and said power terminal;
- and
- connecting an output of said second-voltage-threshold means to said input of said signal-latching means;
- said second-voltage-threshold-sensitive means operating to control said signal-latching means to cause said signal-latching means to apply said test-mode signal to said testing-circuitry upon the occurrence of said second signal, and when said source of operating voltage has risen to said second higher voltage, and said test-mode signal being thereafter maintained independent of said first and second signals received respectively by said first and second terminals.
A method for testing an operational-circuit using a test-circuit, wherein said test-circuit is enabled upon receiving a test-mode signal, comprising the steps of:
- providing a voltage source of a first polarity, said voltage source having an output voltage that is zero at a beginning of a time-interval, said output voltage progressively increasing during said time-interval, first to a low voltage and then to a high voltage;
- providing a first terminal that receives a first signal of an opposite polarity generally coincident with said beginning of said time-interval;
- providing a second terminal that receives a second signal of said opposite polarity at a time within said time-interval at which said output voltage of said voltage source is generally equal to said high voltage;
- providing first-voltage-threshold-sensitive means;
- connecting an output of said first-voltage-threshold-sensitive means to provide said test-mode signal to said test-circuitry;
- connecting an input of said first-voltage threshold-sensitive means to receive a voltage difference between said first terminal and said voltage source;
- said first-voltage-threshold-sensitive means operating to apply said test-mode signal to said testing-circuit when said output voltage of said voltage source generally equals said low voltage;
- providing signal-latching means having an input and an output;
- connecting said output of said signal-latching means to said testing-circuit;
- providing second-voltage-threshold-sensitive means;
- connecting an input of said second-voltage-threshold means to receive a voltage difference between said second terminal and said power supply, and
- connection an output of said second-voltage-threshold means said input of said signal-latching means;
- said second-voltage-threshold-sensitive means operating to control said signal-latching means to cause said signal-latching means to apply said test-mode signal to said testing-circuit upon the occurrence of said second signal.
Dependencies are inferred from the claim text.