Charge pump circuit, PLL circuit with charge pump circuit, and semiconductor integrated circuit with charge pump circuit
AssigneeFujitsu Limited
InventorMasaaki Okamoto
Life of this patent
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AssigneeFujitsu Limited
InventorMasaaki Okamoto
Estimating the term…
A charge pump circuit has a first transistor connected to a first power source and having a control electrode to receive a first control signal; a second transistor connected to a second power source and having a control electrode to receive a second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide a VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. This charge pump circuit realizes a stable PLL operation for a wide range of VCO input voltages, has little data rate dependency, and operates at high speed.
A charge pump circuit comprising:
A phase-locked loop circuit having a phase comparator for comparing phases of reference and output signals with each other, a charge pump circuit for receiving first and second control signals from the phase comparator and providing corresponding signals, a low-pass filter for filtering an output of the charge pump circuit into a VCO input signal, and a voltage-controlled oscillator for generating a signal whose frequency is determined by the VCO input signal, wherein the charge pump circuit comprises:
A semiconductor integrated circuit having a multiplexer for multiplexing low-speed parallel data composed of a plurality of bits into high-speed serial data, a clock generator for receiving a reference clock signal and generating a clock signal for the multiplexer, a demultiplexer for demultiplexing high-speed serial data into low-speed parallel data composed of a plurality of bits, and a clock recovery circuit for receiving the high-speed serial data and generating a clock signal for the demultiplexer, wherein the clock recovery circuit includes a phase-locked loop circuit having a phase comparator for comparing the phases of reference and output signals with each other, a charge pump circuit for receiving first and second control signals from the phase comparator and providing corresponding signals, a low-pass filter for filtering an output of the charge pump circuit into a VCO input signal, and a voltage-controlled oscillator for generating a signal whose frequency is determined by the VCO input signal, wherein the charge pump circuit comprises:
Dependencies are inferred from the claim text.