Device for switching among clock signals allocated to a plurality of users

A switching arrangement for selecting a clock signal for a digital circuit, said switching arrangement having a plurality of users, each user emitting a selection signal, indicating selection of that user, and a clock signal, said switching arrangement comprising:

• a plurality of selection circuits equal in number and respectively allocated to said users, each selection circuit having a first input supplied with the selection signal of its allocated user, a second input supplied with the clock signal of its allocated user, a third input, and first and second outputs;
• each selection circuit further including means for producing a sampled selection criterion and means for producing a delayed selection criterion derived from said sampled selection criterion, said sampled selection criterion and said delayed selection criterion comprising selection criteria and being present at said first output and an activity signal being present at said second output;
• means for providing said activity signal at said second output from said delayed selection criterion;
• the third input of each selection circuit being connected to the first output of each of the other selection circuits;
• each selection circuit further including means for enabling production of said selection criteria only in the presence of the selection signal from its allocated user and the absence of any selection criteria at its third input;
• the digital circuit connected to the second outputs of all of said selection circuits and being supplied with the activity signal from the selection circuit allocated to a selected user;
• and
• clock switching means, having a first set of inputs connected to said users and receiving the respective clock signals therefrom and a second set of inputs connected to the first outputs of said selection circuits for receiving said selection criteria therefrom, for switching one clock signal, emitted by a user which has emitted a selection signal, through as a selected clock signal to said digital circuit dependent on said selection criteria.