Address bit latching input circuit

An address bit input circuit comprising:

• first, second, and third input terminals for respectively receiving an input address bit signal having FIRST and SECOND levels, an enable signal having LOW and HIGH levels, and a latch bar signal;
• first, second, and ground power supply terminals for respectively receiving first, second, and ground power supply potentials, the second power supply potential being between the first power supply potential and ground;
• an internal node having an internal node potential;
• an input switching circuit responsive to the address bit signal, enable signal, and the latch bar signal for selectively (i) coupling the internal node to the first input terminal when the enable signal is HIGH so the internal node potential responds to the input address bit signal, and (ii) coupling the internal node to the second power supply terminal when the enable signal is LOW;
• an output terminal;
• and
• a latching circuit coupled to the enable signal, latch bar signal, internal node potential, and output terminal for selectively generating at the output terminal a (i) a latched address output signal responsive to the internal node potential when the enable signal is HIGH and (ii) a standby output signal when the enable signal is LOW.