System and method for fault analysis of semiconductor integrated circuit
AssigneeNEC Corporation
InventorsToyokazu Nakamura, Yasuko Hanagama, Tohru Tsujide, Kenji Morohashi
Life of this patent
Estimating the term…
Loading patent…
AssigneeNEC Corporation
InventorsToyokazu Nakamura, Yasuko Hanagama, Tohru Tsujide, Kenji Morohashi
Estimating the term…
In a fault analysis of large-scale integrated (LSI) circuits, a potential distribution image of a non-defective product and another potential distribution image of a defective product are displayed alternately and continuously in time, so that it is possible to acquire in real time an image of any location within a whole surface of the LSI chip. As a result, it can be viewed as if the potential distribution image of the non-defective product and the potential distribution image of the defective product are overlapped or superimposed with over time. Accordingly, a different portion between the non-defective and defective potential distribution images can be seen distinguishably from a coincident portion between the non-defective and defective potential distribution images, so that it is possible to trace the different portion in real time.
A fault analysis system for a semiconductor integrated circuit, for locating a fault portion in the semiconductor integrated circuit, comprising:
A fault analysis method for a semiconductor integrated circuit, for locating a fault portion in the semiconductor integrated circuit, said method comprising steps of:
Dependencies are inferred from the claim text.