US 5,703,489 AGranted

Timing calibration circuit and method for test signals

AssigneeAdvantest Corporation

InventorShinichiro Kuroe

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Abstract

A timing calibration circuit includes a plurality of variable delay circuits each of which is assigned to one of test signal paths to regulate a phase delay time for a signal passing therethrough, a multiplexer for selecting one of the test signal paths whose inputs are connected to outputs of drivers, a signal path whose one end is connected to all of test contactors and the other end is connected to the multiplexer, a counter for measuring phase delay times in a first feedback loop which does not include the signal path and a second feedback loop which includes the signal path with respect to each of the test signal paths. The counter measures a phase delay time for the first feedback loop to determine a reference value so that a phase delay time in the first feedback loop for other test signal paths is adjusted by the variable delay circuit to be equal to the reference value, and the counter measures a phase delay time for the second feedback loop to determine a calibration value for each of the test signal paths and record the calibration value.

Claims8

Dependent claims

A timing calibration circuit for test signals to be used in a semiconductor test system having a timing generator (8), a plurality of test signal paths each having a wave-formatter (7) for shaping waveforms of a test signal (3) from the timing generator (8), a driver (5) for determining an amplitude of the test signal from the wave-formatter (7) and a test contactor (2) connected to the driver (5) for establishing an electronic connection between a corresponding pin of a semiconductor device (1) to be tested and said semiconductor test system, said timing calibration circuit comprising:

a plurality of variable delay circuits (6) each of which is assigned to one of said test signal paths, each of said variable delay circuits varying a phase delay time for a signal passing therethrough;
a multiplexer (16) for selecting one of said test signal paths for said timing calibration, inputs of said multiplexer being connected to outputs of said drivers;
a first signal path (12.sub.1) having a point of connection (G) at one end which is connected to all of said test contactors (2) and another end which is connected to said multiplexer (16);
a means for measuring a phase delay time for signal propagation through a second signal path (12.sub.2) connected between said multiplexer (16) and said measuring means when a pulse signal originated by said timing generator for said timing calibration propagates through said second signal path;
said multiplexer (16) selectively forming a first feedback loop and a second feedback loop with respect to each of said test signal paths, said first feedback loop including said driver (5), said test contactor (2) and said first signal path (12.sub.1) while said second feedback loop including said driver (5);
said measuring means measuring a phase delay time for said first feedback loop to determine a reference value so that a phase delay time in said first feedback loop for other test signal paths is adjusted by said variable delay circuit to be equal to said reference value, said measuring means measuring a phase delay time for said second feedback loop to determine a calibration value, said calibration value for each of said test signal paths being recorded to be used for later calibration procedures.

3 more elements

A timing calibration method for test signals to be used in a semiconductor test system having a timing generator (8), a plurality of test signal paths each having a wave-formatter (7) for shaping waveforms of a test signal (3) from the timing generator (8), a driver (5) for determining an amplitude of the test signal from the wave-formatter (7) and a test contactor (2) connected to the driver (5) for establishing an electronic connection between a corresponding pin of a semiconductor device (1) to be tested and said semiconductor test system, said timing calibration method comprising the following steps of:

providing a plurality of variable delay circuits each of which is assigned to one of said test signal paths, each of said variable delay circuits varying a phase delay time for a signal passing therethrough;
selecting one of said test signal paths by a multiplexer, inputs of said multiplexer being connected to outputs of said drivers;
forming a first signal path having a point of connection at one end which is connected to all of said test contactors and another end which is connected to said multiplexer;
measuring a phase delay time for signal propagation through a second signal path connected between said multiplexer and a counter which measures the phase delay time when a pulse signal originated by said timing generator propagates through said second signal path for a timing calibration purpose;
selectively forming a first feedback loop and a second feedback loop with respect to each of said test signal paths, said first feedback loop including said driver, said test contactor and said first signal path while said second feedback loop including said driver;
measuring a phase delay time for said first feedback loop to determine a reference value so that a phase delay time in said first feedback loop for other test signal paths is adjusted by said variable delay circuit to be equal to said reference value;
and
measuring a phase delay time for said second feedback loop to determine a calibration value, said calibration value for each of said test signal paths being recorded to be used for later calibration procedures.

5 more elements

Dependencies are inferred from the claim text.