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AssigneeMicrochip Technology Incorporated
InventorsStephen C. Hinkle, Richard Hull
Estimating the term…
A circuit for providing protection from effects of electromagnetic interference (EMI) at input pins and internal nodes of an integrated circuit (IC) includes a regenerative comparator (Schmitt trigger) to perform triggering functions in response to input pulses applied to the input pin, resulting in hysteresis between high and low trigger voltages. The hysteresis extends durations of false pulses induced by presence of EMI at the input pin. A filter is coupled to the regenerative comparator, with a filter response time with a duration at least as great as the expected largest duration of EMI-induced false pulses including extended duration attributable to the hysteresis, for filtering out the EMI-induced false pulses. A pulse generator is coupled to the filter, for generating a pulse for application to the IC whenever a pulse applied to the input pin has a duration exceeding the duration of the filter time constant. The filter circuit also includes apparatus for changing a logic state of EMI-sensitive internal nodes of the IC which have relatively high RC time constants, are at a logic "1" state, and are in signal paths of the IC which determine operation of the IC, and converting the logic "1" state to a logic "0" state whenever EMI is present in the IC. The EMI-sensitive internal nodes of the IC electrically isolates the internal nodes, e.g., to inhibit them from discharging in the presence of EMI in the IC. The electrical isolation is provided by a resistor or a diode coupled between an internal node and a point of electrical ground reference. The internal nodes are EMI sensitive, each having a relatively high RC time constant for charging to a predetermined voltage level representing a logic value, located in a signal path of the IC enabled by IC circuit conditions to determine IC operation, and normally held at a logic "1" value during IC operation. When EMI detected in the IC, the logic value of the nodes is changed to logic "0".
A method for providing electromagnetic interference (EMI) immunity for an integrated circuit (IC), comprising the steps of:
A circuit for providing protection from effects of electromagnetic interference (EMI) at input pins and internal nodes of an integrated circuit (IC), comprising:
A protection circuit coupled between an input pin and internal circuitry of an integrated circuit (IC) for protecting the IC from the effects of electromagnetic interference (EMI), the input pin for receiving an input signal and the protection circuitry for providing an output signal to the internal circuitry of the IC indicative of the input signal substantially excluding the effects of EMI, the protection circuit comprising:
A circuit for protecting an integrated circuit (IC) from electromagnetic interference (EMI) so as to avoid an inappropriate response by the IC to a false pulse induced at an input pin of the IC by an EMI event, the protection circuit comprising pulse width analyzer means coupled to the input pin and to internal circuitry of the IC for determining the duration of such a false pulse induced at said input pin, and filter means coupled to said pulse width analyzer means and responsive to a determination of duration of each such false pulse by said pulse analyzer means for setting response time of the filter means in accordance therewith to filter out the respective such false pulse before said internal circuitry of the IC can respond thereto, and further including electrical discharge means coupled to an internal node of the IC and responsive to occurrence of an EMI event for inhibiting discharge of the internal node upon said occurrence.
Dependencies are inferred from the claim text.