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US 5,703,392 AGranted
Minimum size integrated circuit static memory cell
OwnerJeng-Jong Guoinventor
Life of this patent
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Abstract
A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.
Claims11
A semiconductor static memory cell comprising:
- two cross-coupled inverters with a first inverter and a second inverter, each having a pull-up load device and a pull-down MOSFET with a drain, a source and a gate,
- an output node of the first inverter of said cross-coupled inverters, where the drain of said pull-down MOSFET is connected to the load device, being coupled to the gate of the MOSFET of the second inverter of said cross-coupled inverters,
- an output node of the second inverter of said cross-coupled inverters being coupled to the gate of the MOSFET of said first inverter,
- a first MOSFET pass transistor having a gate connected to a word line, and two other electrodes, a source and a drain, connected between the output node of said first inverter and a bit line,
- a second MOSFET pass transistor having a gate connected to said word line, and two other electrodes, a source and a drain, connected between the output node of said second inverter and a complementary bit line,
- said first and second MOSFET pass transistors having a threshold voltage higher than said pull-down MOSFET, and
- having a width-to-length ratio of the gate of the pull-down MOSFET less than 2.5 times the width-to-length ratio of the gate of the pass transistor.
4 more elements
A semiconductor static memory cell comprising:
- two cross-coupled inverters, each having a pull-up load device and a pull-down MOSFET with a drain, a source and a gate,
- an output node of the first inverter of said cross-coupled inverters, where the drain of said pull-down MOSFET is connected to the load device, being coupled to the gate of the MOSFET of the second inverter of said cross-coupled inverters,
- a second output node of the second inverter of said cross-coupled inverters being coupled to the gate of the MOSFET of said first inverter,
- a first MOSFET pass transistor having a gate connected to said word line, and two other electrodes, a source and a drain, connected between the output node of the said first inverter and a bit line,
- a second MOSFET pass transistor having a gate connected to said word line, and two other electrodes, the source and the drain, connected between the output node of said second inverter and a complementary bit line,
- said first and second MOSFET pass transistors having a lower transconductance parameter than the transconductance parameter of the pull-down MOSFET, and
- said gate of said pull-down MOSFET having a ratio of width to length of said gate of said pull-down MOSFET less than 2.5 times the ratio of width to length of the gate of said pass transistor.
4 more elements
Dependencies are inferred from the claim text.