Vertical IGFET configuration having low on-resistance and method
AssigneeMotorola, Inc.
InventorsLynnita K. Knoch, Pak Tam
Life of this patent
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Abstract
A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.
Claims17
A vertical IGFET configuration having low on-resistance comprising a plurality of stripes formed on one surface of a semiconductor substrate and a drain electrode formed on an opposite surface of the semiconductor substrate, the plurality of stripes extending into the semiconductor substrate and having a non-linear shape that increases channel density thereby providing the low on-resistance, wherein each of the plurality of stripes includes a source region within a base region, and wherein the plurality of stripes is coupled together to form a single base configuration.
An IGFET device having a plurality of stripe regions on one surface of a semiconductor substrate and a drain electrode on an opposite surface of the semiconductor substrate, comprising a configuration of the plurality of stripe regions to increase channel density, wherein each of the plurality of stripe regions has a pattern including elongated portions and contact cut-out portions, the contact cut-out portions wider than the elongated portions thereby increasing channel density, and wherein the plurality of stripe regions includes a plurality of source regions within a plurality of base regions, and wherein the plurality of base regions is coupled together to form a single base configuration.
A vertical IGFET arrangement having low on-resistance comprising:
- a semiconductor substrate having a first surface and a second surface opposite the first surface;
- a plurality of well regions formed in the semiconductor substrate and extending from the first surface, each of the plurality of well regions having a non-linear stripe shape including a first portion having a first width and a second portion having a second width less than the first width and wherein each of the plurality of well regions is tied together to form a common base configuration;
- a source region formed within each of the plurality of well regions;
- a common drain electrode in contact with the second surface;
- and
- an insulated gate region formed between adjacent well regions.
A method for forming a vertical IGFET device having low on-resistance comprising the steps of:
- providing a semiconductor substrate having a first surface and a second surface opposite the first surface;
- forming a plurality of well regions in the semiconductor substrate extending from the first surface, each of the plurality of well regions having non-linear stripe shape, and wherein each of plurality of well regions is tied together to form a common base configuration;
- forming a source region within each of the plurality of well regions;
- forming an insulated gate region on the first surface;
- forming a source electrode in contact with the source region within each of the plurality of well regions;
- and
- forming a common drain electrode in contact with the second surface.
Dependencies are inferred from the claim text.