Blending integrated circuit technology

A method of forming logic and memory devices in the same semiconductor substrate using a triple-well structure having N-well regions, P-well regions, and a P-well-in-N-well regions, comprising the steps of:

• doping said substrate by ion implanting a first conductivity-imparting dopant;
• ion implanting a second conductivity-imparting dopant into said N-well and P-well-in-N-well regions;
• forming a first insulating layer over said substrate;
• forming a second insulating layer over said first insulating layer;
• forming openings in said first and second insulating layers by patterning said first and second insulating layers to expose regions of said substrate in which field isolation regions are desired to be formed;
• forming field isolation regions in said openings;
• removing said first and second insulating layers;
• ion implanting a third conductivity-imparting dopant in said P-well and said P-well-in-N-well regions;
• driving in said first, second and third-conductivity-imparting dopants by heating said substrate to a temperature of between about 900.degree. and 1200.degree. C.;
• forming said logic devices in said N-well regions and said P-well regions;
• and
• forming said memory devices in said P-well-in-N-well regions.

A method of forming semiconductor logic devices and memory devices on a single semiconductor substrate, in a logic region and memory region, respectively, comprising the steps of:

• providing a semiconductor substrate having a first conductivity type dopant;
• forming a triple-well structure in said semiconductor substrate, having N-well regions, P-well regions, and P-well in N-well regions;
• forming field isolation regions in said semiconductor substrate, in both said logic and memory regions;
• forming a cell for said memory device in said P-well in N-well region of said memory region;
• performing a channel implant in said substrate for each of said logic and memory devices;
• forming a primary gate oxide over said substrate for each of said logic and memory devices;
• forming a gate over each said primary gate oxide;
• forming lightly doped drain (LDD) regions in said substrate, using said gate as a mask;
• forming sidewall spacers on the vertical sides of each said gate;
• forming heavily doped source and drain regions adjacent to said LDD regions, using said gate and said sidewall spacers as a mask;
• forming an inter-level dielectric layer over said logic and memory devices;
• forming contact openings in said inter-level dielectric layer over contact regions of said logic and memory devices;
• depositing a metal layer over said inter-level dielectric layer and in said openings to make contact to said contact regions;
• and
• completing said memory and logic devices.