US 5,702,964 AGranted

Method for forming a semiconductor device having a floating gate

AssigneeLG Semicon Co., Ltd.

InventorByung-Il Lee

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Abstract

A method for forming of a semiconductor device having a transistor with a floating gate includes the steps of forming a first insulating layer and a first conductive layer on a surface of the substrate, patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes and implanting ions on the cell forming area, forming a second insulating layer on the resulting surface so that the second insulating layer fills a space between the preliminary floating gate electrodes, forming a third insulating layer on the resulting surface, forming a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second conductive layer, forming a gate electrode by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode pattern has a first distance between the gate lines in a portion to be a contact hole, and a second distance between the gate lines is arranged in another portion, the first distance being wider than the second distance, and forming a floating gate electrode by patterning the third insulating layer and the second conductive layer.

Claims20

Dependent claims

A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) forming a first insulating layer and a first conductive layer on a surface of the substrate;
(b) patterning the first conductive layer on a cell forming area for forming preliminary floating gate electrodes spaced by a distance and implanting ions on the cell forming area;
(c) forming a second insulating layer on the resulting surface formed after step (b) and etching the second insulating layer so that the second insulating layer remains on a side wall of the preliminary floating gate electrodes and fills the distance between preliminary floating gate electrodes;
(d) forming a third insulating layer on the resulting surface formed after step (c);
(e) forming a second conductive layer on the third insulating layer;
(f) forming a fourth insulating layer on the second conductive layer;
(g) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns have a first distance between the gate patterns in a portion to be a contact hole, and a second distance between the gate patterns is arranged in another portion, the first distance being wider than the second distance;
(h) forming a floating gate electrode by patterning the third insulating layer and the preliminary floating gate electrodes using the gate electrode patterns as a mask;
(i) forming source and drain regions by ion implantation;
(j) forming a fifth insulating layer and anisotropically etching the fifth insulating layer for forming a contact hole;
and
(k) filling the contact hole with a third conductive layer, and patterning the third conductive layer into wiring.

9 more elements

A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) forming a first insulating layer and a first conductive layer on a surface of the substrate;
(b) patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes spaced by a distance and implanting ions on the cell forming area;
(c) forming a second insulating layer on the resulting surface formed after step (b) so that the second insulating layer fills the distance between the preliminary floating gate electrodes;
(d) forming a third insulating layer on the resulting surface formed after step (c);
(e) forming a second conductive layer on the third insulating layer;
(f) forming a fourth insulating layer on the second conductive layer;
(g) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns have a first distance between the gate patterns in a portion to be a contact hole, and a second distance between the gate patterns is arranged in another portion, the first distance being wider than the second distance;
and
(h) forming a floating gate electrode by patterning the third insulating layer and the preliminary floating gate electrodes.

6 more elements

A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) after forming a isolation region in the semiconductor substrate, forming a first insulating layer and a first conductive layer on the resulting surface of the substrate;
(b) forming preliminary floating gate electrodes by patterning the first conductive layer on a cell forming area, and implanting ions on the cell forming area;
(c) forming a second insulating layer on the resulting surface formed after step (b) and etching the second insulating layer back so that it remains on the side walls of the preliminary floating gate electrodes, thus filling the distance between the preliminary floating gate electrodes;
(d) forming a third insulating layer on the resulting surface formed after step (c), forming a second conductive layer on the third insulating layer, and forming a fourth insulating layer on the second conductive layer;
(e) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns are arranged in such a layout that a wide distance between the gate patterns is arranged in a portion to be a contact hole, and a narrow distance between the gate patterns is arranged in another portion;
(f) forming a floating gate electrode by patterning the third insulating layer and the second conductive layer using the gate electrode as mask, and forming a source and drain region by ion implantation;
(g) forming a fifth insulating layer and etching the fifth insulating layer back anisotropically, thus forming a contact hole;
and
(h) filling the cantact hole with a third conductive layer, and patterning the third conductive layer into wiring.

6 more elements

Dependencies are inferred from the claim text.