US 5,702,962 A · Fabrication process for a static induction transistor

Abstract

A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C. in a hydrogen atmosphere in a state that the tops of the projections between the recesses have been brought into contact with the metal layer provided on the underside of the N.sup.+ substrate, whereby the N.sup.- substrate and the N.sup.+ substrate are joined to each other.

Claims15

Dependent claims

A process for fabricating a semiconductor device, which comprises the steps of:

providing first and second semiconductor substrates of the same conductive type;
selectively forming gate regions composed of a semiconductor having a conductive type different from that of the first semiconductor substrate in one principal surface of the first semiconductor substrate with portions of said one principal surface of the first semiconductor substrate exposed between the gate regions;
forming a metal layer and/or a metal silicide layer on at least one of at least regions of one principal surface of the second semiconductor substrate, to which portions of said one principal surface of the first semiconductor substrate exposed between the gate regions are opposite, and said one principal surface portions of the first semiconductor substrate exposed between the gate regions;
and
joining said one principal surface of the first semiconductor substrate to said one principal surface of the second semiconductor substrate through the metal layer and/or the metal silicide layer.

2 more elements

Dependencies are inferred from the claim text.

Fabrication process for a static induction transistor

Life of this patent

Fabrication process for a static induction transistor

Life of this patent

Abstract

Claims15