Method of making buried metallization structure
AssigneeLSI Logic Corporation
InventorGobi R. Padmanabhan
Life of this patent
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AssigneeLSI Logic Corporation
InventorGobi R. Padmanabhan
Estimating the term…
Disclosed is an IC structure providing conductive lines for routing within a semiconductor substrate immediately below the level of the active IC devices. These "buried" conductive lines are insulated from each other by dielectric regions formed as an insulating plane immediately below the active devices and resembling a conventional silicon on insulator (SOI) structure. Within this plane, however, the buried conductive lines provide routes between various active device elements to form some circuit connections such as intracell connections for a gate array. Thus, the buried conductive lines replace some routing from the metallization/dielectric layer stack on top of the active region.
A process of forming a buried interconnect providing a conductive pathway between multiple active devices provided in an active layer of a semiconductor substrate having a surface, the buried interconnect being located beneath the surface of said semiconductor substrate, the process comprising the following steps:
Dependencies are inferred from the claim text.