Mask for optical lithography using phase shift masking and integrated circuit produced therefrom
AssigneeAdvanced Micro Devices, Inc.
InventorChristopher A. Spence
Life of this patent
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Abstract
A method of performing poly level lithography in manufacturing an integrated circuit using a phase shift mask in a step and repeat optical tool where the phase assignment for said phase shift mask is determined by a technique which determines, without assignment conflict, the Intersection of the gate pattern with the active gate pattern and which divides the Intersection into categories of stacks where a slightly different phase assignment rules is employed for the different stacks.
Claims31
An integrated circuit being formed from a mask which is manufactured by the process of:
- providing a mask substrate;
- forming a gate level pattern on the mask substrate;
- identifying regions of the mask substrate which correspond to active regions of the integrated circuit and identifying one or more portions of the gate level pattern which overlap with the active regions of the integrated circuit;
- and
- forming phase shift regions of different phases on opposite sides of at least one identified portion so as to cause light transmitted through the opposite sides to destructively interfere with each other.
An integrated circuit (IC) being formed from an i-line stepper lithography method for phase shift mask patterning for forming the levels of the IC on a semiconductor wafer, said lithography method including use of different masks to pattern the layout of different levels, one such level being the gate level and a second such level being the active regions, said active regions being spatially defined by an active region layout pattern, said gate level being spatially defined by a gate level pattern having first and second gate level layout portions, said first gate level layout portion being a standard non-phase shift mask pattern having opaque and non-opaque regions and said second gate level layout portion having areas containing phase shift regions, wherein said method comprises:
- performing a comparative analysis of said active region layout pattern and said gate level layout portion to spatially establish Intersection regions corresponding to the regions on the IC where said active region layout pattern and said first gate level layout portion overlay, said Intersection regions being rectangles having a pair of parallel long sides and a pair of parallel short sides;
- constructing a transmissive light field phase shift mask (PSM) having various phase shifted regions and opaque regions for patterning said gate level, said PSM comprising said gate level layout pattern, said gate level layout pattern being identical to said first gate level layout portion except in the regions on said PSM corresponding to said Intersection regions, said gate level layout pattern including zero degree phase shift regions which are contiguous with one of said parallel long sides of said regions corresponding to Intersection regions and a 180 degree phase shift region contiguous with the other of said parallel long sides of said regions corresponding to said Intersection regions, said opaque pattern of said transmissive light field PSM corresponding to said Intersection regions and to said opaque regions of said first gate level layout portion;
- and
- aligning said PSM in said i-line stepper and exposing a positive resist on said wafer with a light source directed through said transmissive light field PSM by focusing with a lens system of said i-line stepper said light which transmits through said PSM onto said positive resist on said wafer.
A mask for producing a gate level pattern on a substrate of an integrated circuit, comprising:
- a light-transmissive mask substrate;
- an opaque gate level pattern formed on the mask substrate;
- phase shift regions of different phases formed on opposite sides of those portions of the opaque gate level pattern which overlap with active regions of the integrated circuit, but not on opposite sides of those portions of the opaque gate level pattern which do not overlap with active regions of the integrated circuit.
Dependencies are inferred from the claim text.