Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorsTadashi Mitsui, Katsuhiko Hieda
Estimating the term…
Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.
A semiconductor integrated circuit fabrication process comprising simultaneously forming a circuit pattern feature and a photolithographic alignment mark on a semiconductor wafer by etching, said alignment mark being formed as a composite mark comprising a plurality of small marks, said small marks being sufficiently close in shape, size and spacing to said circuit pattern feature that an etch rate within an area of said circuit pattern feature and an etch rate within an area of each small mark are substantially the same.
Dependencies are inferred from the claim text.