US 5,694,377 AGranted

Differential time interpolator

AssigneeLTX Corporation

InventorEric B. Kushnick

Life of this patent

Estimating the term…

Loading patent…

Abstract

The disclosed apparatus includes first and second delay lines, the first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, and the second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, and each of the output taps has an associated delay interval. A first signal representative of a first event is applied to the input tap of the first delay line, and a second signal representative of a second event is applied to the input tap of the second delay line. The disclosed apparatus further includes a set of n latches L.sub.1, L.sub.2, . . . L.sub.n, and a set of n delay units D.sub.1, D.sub.2, . . . D.sub.n. The output signals generated by taps F.sub.i and S.sub.i are applied to a first input terminal and a second input terminal, respectively, of latch L.sub.i. Each of the latches generates a latch signal by using one of the signals applied to its first and second input terminals to latch the signal applied to the other of its first and second input terminals. The latch signal generated by latch L.sub.i is applied to the delay unit D.sub.i. Each of the delay units delays its latch signal by an associated latch delay interval and thereby generates a code signal. The associated latch delay interval of delay unit D.sub.i is at least as large as a difference between the output delay intervals associated with the nth and ith output taps S.sub.n and S.sub.i of the second delay line.

Claims30

Dependent claims

An apparatus for measuring a time interval between a first event and a second event, said apparatus comprising:

A. a first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, each of said output taps having an associated output delay interval, said input tap being coupled to receive a first signal representative of said first event, each of said output taps generating an output signal representative of said first signal after being delayed by its associated output delay interval;
B. a second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, each of said output taps having an associated output delay interval, said input tap being coupled to receive a second signal representative of said second event, each of said output taps generating an output signal representative of said second signal after being delayed by its associated output delay interval;
C. a set of n latch elements L.sub.1, L.sub.2, . . . L.sub.n, each of said latch elements having a first input terminal and a second input terminal, an ith one of said latch elements L.sub.i having its first input terminal coupled to receive the output signal generated at the ith output tap F.sub.i of said first delay line and its second input terminal coupled to receive the output signal generated at the ith output tap S.sub.i of said second delay line for all i from one to n, each of said latch elements including means responsive to one of the signals received at its first and second input terminals for latching the other of the signals received at its first and second input terminals and thereby generating a latch signal;
and
D. delay means for receiving the latch signals generated by all of said latch elements and including means for generating therefrom a delayed signal, said delayed signal being representative of respective ones of the latch signals generated by said latch elements as delayed by an associated delay interval, wherein the delay interval associated with the latch signal generated by the ith latch element L.sub.i is at least as large as a difference between the output delay intervals associated with the nth and ith output taps S.sub.n and S.sub.i of said second delay line for all i from one to n.

2 more elements

An event time stamper for measuring a duration of an interval, comprising:

A. means for receiving a periodic clock signal characterized by an oscillation frequency f.sub.c and a corresponding period T.sub.c and including means for counting a number of periods T.sub.c of said clock signal occurring during said interval;
and
B. time interpolator means for measuring a duration of a remainder portion of said interval occurring during a fractional portion of a single period T.sub.c of said clock signal, comprising:
i. a first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, each of said output taps having an associated output delay interval, said input tap being coupled to receive a first signal representative of a beginning of said remainder portion, each of said output taps generating an output signal representative of said first signal after being delayed by its associated output delay interval;
ii. a second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, each of said output taps having an associated output delay interval, said input tap being coupled to receive a second signal representative of an ending of said remainder portion, each of said output taps generating an output signal representative of said second signal after being delayed by its associated output delay interval;
iii. a set of n latch elements L.sub.1, L.sub.2, . . . L.sub.n, each of said latch elements having a first input terminal and a second input terminal, an ith one of said latch elements L.sub.i having its first input terminal coupled to receive the output signal generated at the ith output tap F.sub.i of said first delay line and its second input terminal coupled to receive the output signal generated at the ith output tap S.sub.i of said second delay line for all i from one to n, each of said latch element including means responsive to one of the signals received at its first and second input terminals for latching the other of the signals received at its first and second inputs and thereby generating a latch signal;
and
iv. delay means for receiving the latch signals generated by all of said latch elements and including means for generating therefrom a delayed signal, said delayed signal being representative of respective ones of the latch signals generated by said latch elements as delayed by an associated delay interval, wherein the delay interval associated with the latch signal generated by the ith latch element L.sub.i is at least as large as a difference between the output delay intervals associated with the nth and ith output taps S.sub.n and S.sub.i of said second delay line for all i from one to n.

5 more elements

Dependencies are inferred from the claim text.