High speed data access apparatus for paged memory device

A high speed data access apparatus for memory, comprising:

• an ATD signal generating means for detecting each transition of an address signal and a page address signal after being enabled by the chip enable signal and for generating each of an ATD signal and a page ATD signal;
• a first control signal generating means for generating a sense amplify control signal using an ATD signal outputted from the ATD signal generating means after being enabled by an enable signal inputted thereto from the output enable buffer and generating a buffer control signal using an ATD signal and a page address transition signal respectively outputted from the ATD signal generator;
• a second control signal generating means for generating a latch control signal using a page address signal outputted from the page address buffer;
• a page predecoder for predecoding a page address signal outputted from the page address buffer;
• a predecoder for decoding an address signal outputted from the address buffer;
• a low decoder and a column decoder each for decoding a signal outputted from the predecoder, designating and withdrawing data stored previously in a memory cell and;
• a sense amplifier, after being enabled by a sense amplify enable signal outputted from the first control signal generator, for amplifying to a certain level the page data applied thereto using the low decoder and the column decoder;
• a latch for temporarily storing therein the data outputted from the sense amplifier after being enabled by a latch signal outputted from the second control signal generator;
• a page decoder for decoding a signal outputted from the page predecoder and selectively outputting therefrom the page data outputted from the latch;
• and
• an output buffer for buffering the page data outputted from the page decoder after being enabled by a buffer control signal outputted from the first control signal generator and outputting the buffered page data therefrom.