US 5,692,165 A · Memory controller with low skew control signal

Abstract

An apparatus and a method are provided for delaying or skewing a control signal provided to an electronic device such as a memory device with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to the electronic device substantially equals one or more integral cycles of a clock signal. As a result, the control signal received at the electronic device is substantially aligned with the clock signal. This results in synchronizing or realigning the asynchronously-generated control signal back into a synchronous environment. The apparatus and method have unique applicability when used in memory controllers and the like for handling memory accesses with one or more memory devices, in particular with memory devices having enhanced memory transfer modes or higher transfer speeds, where even a small amount of skew between a control signal and a clock signal may significantly degrade performance. A propagation delay, or delay factor, associated with outputting the control signal to the electronic device is computed based upon the process factor for the apparatus, as well as any temperature and/or voltage variations. In addition, the delay factor may be modified dynamically to account for real-time voltage and/or temperature variations.

Claims29

Dependent claims

An apparatus for controlling a memory in response to an access request from a processor, the apparatus and the memory each electrically coupled to the processor across a bus of the type having information transferred thereon that is aligned with a clock signal, the memory of the type for receiving at least one strobe control signal, the apparatus comprising:

(a) a memory control circuit for providing control signals to the memory in response to an access request, wherein the control signal generating circuit generates a strobe enable signal;
and
(b) a strobe generating circuit, electrically coupled to receive the strobe enable signal and the clock signal, for providing a strobe control signal to the memory, the strobe generating circuit including:
(1) a first delay for delaying the clock signal by a first alignment delay value to generate a strobe clock signal;
(2) a second delay for delaying the strobe enable signal by a second alignment delay value to generate a delayed strobe enable signal;
and
(3) an output device, electrically coupled to the memory, for gating the strobe clock with the delayed strobe enable signal to thereby provide the strobe control signal to the memory;
wherein the first alignment delay value is selected to align the strobe control signal with the clock signal and the second alignment delay value is selected to align the delayed strobe enable signal with the strobe clock.

5 more elements

A method of aligning a strobe control signal and a clock signal received by a memory device, that is coupled to a processor across a bus, comprising the steps of:

(a) generating a strobe enable signal in response to an access request from the processor;
(b) determining a first alignment delay having a value that, when summed with the propagation delay of the strobe control signal, is related to at least one integral cycle of the clock signal;
(c) determining a second alignment delay;
(d) delaying the clock signal by the first alignment delay to generate a strobe clock signal and delaying the strobe enable signal by the second alignment delay to generate a delayed strobe enable signal;
(e) gating the strobe clock with the delayed strobe enable signal to thereby provide the strobe control signal to the memory device such that the strobe control signal is aligned with the clock signal at the memory device;
wherein the first alignment delay is determined so as to align the strobe control signal with the clock signal and the second alignment delay value is determined so as to align the delayed strobe enable signal with the strobe clock.

3 more elements

Dependencies are inferred from the claim text.

Memory controller with low skew control signal

Life of this patent

Memory controller with low skew control signal

Life of this patent

Abstract

Claims29