Semiconductor device with high speed operation and high integration
AssigneeKabushiki Kaisha Toshiba
InventorHisato Oyamatsu
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Abstract
A semiconductor device manufactured by isolating an element by forming an insulating film on the surface of a semiconductor substrate at an element isolation region, selectively forming a resist film at a second region on the surface of the semiconductor substrate by photolithography, high speed operation having priority over high integration in the second region, and selectively implanting impurity ions as a channel stopper in a first region by using the resist film as a mask, high integration having priority over high speed operation in the first region.
Claims12
A semiconductor device comprising:
- a semiconductor substrate having a first region having a first surface and a second region having a second surface, said first region being adjacent to said second region;
- first MOS transistors formed in the first region;
- a first insulating film formed on the first surface of the semiconductor substrate for isolating the first MOS transistors from each other, the first insulating film having a first width between the first MOS transistors;
- second MOS transistors formed in the second region;
- a second insulating film formed on the second surface of the semiconductor substrate for isolating the second MOS transistors from each other, the second insulating film having a second width between the second MOS transistors, wherein the second width of the second insulating film is wider than the first width of the first insulating film;
- and
- a channel stopper region formed only in the first region by selectively implanting impurity ions through the first insulating film only in the first region, wherein the channel stopper region is isolated from the second MOS transistors in the second region.
A semiconductor device comprising:
- a semiconductor substrate having a first region having a first surface and a second region having a second surface, said first region being adjacent to said second region;
- first and second circuit elements formed in the first region;
- a first element isolation region including a first insulating film formed on the first surface of the semiconductor substrate for isolating the first and second circuit elements, the first element isolation region having a first width X1 between the first and second circuit elements;
- third and fourth circuit elements formed in the second region;
- a second element isolation region including a second insulating film formed on the second surface of the semiconductor substrate for isolating the third and fourth circuit elements, the second element isolation region having a second width X2 between the third and fourth circuit elements, wherein the second width X2 of the second element isolation region is wider than the first width X1 of the first element isolation region;
- and
- a channel stopper region formed only in the first region by selectively implanting impurity ions only in the first region through the first element isolation region, wherein the channel stopper region is isolated from the third and fourth circuit elements in the second region.
Dependencies are inferred from the claim text.