Step-up semiconductor integrated circuit and electronic equipment using the semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a substrate, an insulating layer formed on the substrate;
• a semiconductor layer formed on the insulating layer;
• a plurality of charge boosting elements formed on the semiconductor layer;
• an input terminal for supplying an input voltage to the plurality of boosting elements;
• and an output terminal for providing an output voltage from the plurality of boosting elements;
• wherein each of the boosting elements comprises a rectifying element having an anode terminal and a cathode terminal, and a charge storing element electrically connected to the cathode terminal, each of the boosting elements is electrically connected in series in an anode-to-cathode fashion, and wherein each of the boosting elements is dielectrically isolated from the other boosting elements.

A semiconductor integrated circuit comprising:

• a substrate, an insulating layer formed on the substrate;
• a semiconductor layer formed on the insulating layer;
• and a plurality of charge boosting elements formed on the semiconductor layer;
• wherein each of the boosting elements comprises a rectifying element and a charge storing element electrically connected to the rectifying element, each of the boosting elements is electrically connected in series, each of the boosting elements is dielectrically isolated from the other boosting elements, and each rectifying element comprises a metal-semiconductor junction element.

A semiconductor circuit comprising:

• a clock pulse generating circuit;
• a substrate;
• and a plurality of charge boosting elements formed on the substrate;
• wherein each of the charge boosting elements comprises a rectifying element and a charge storing element electrically connected to the rectifying element, each of the charge boosting elements being electrically connected in series, and wherein the plurality of charge boosting elements are arranged to form first and second charge boosting circuits, the first boosting circuit supplies a boosted output voltage to the clock pulse generating circuit and the second boosting circuit, and the clock pulse generating circuit supplies a boosted clock pulse to the second boosting circuit to enable the second boosting circuit unit to output a large output voltage.

A semiconductor integrated circuit comprising:

• a substrate;
• and a plurality of charge boosting elements formed on the substrate;
• wherein each of the charge boosting elements comprises a rectifying element and a charge storing element electrically connected to the rectifying element, each of the charge boosting elements being electrically connected in series;
• a clock signal generating circuit for supplying a first clock signal and a second clock signal, the second clock signal having a reverse polarity from that of the first clock signal;
• wherein the first clock signal is supplied to a charge storing element connected to an anode of the rectifying elements and the second clock signal is supplied to a charge storing element connected to a cathode of the rectifying elements such that the clock signal generating circuit controls the level of an output voltage from the plurality of boosting elements.

A semiconductor integrated circuit comprising:

• a substrate;
• and a plurality of boosting elements formed on the substrate, each of the boosting elements being electrically connected in series;
• wherein each of the boosting elements comprises a first and a second MOS transistor and a charge storing element having terminals, one of a source and a drain of the first MOS transistor being connected to one of a source and a drain of the second MOS transistor, the other one of the source and the drain of the first MOS transistor being connected to one of the terminals of the charge storing element and constituting a node A, the other one of the source and the drain of the second MOS transistor being connected to the other one of the terminals of the charge storing element and constituting a node B, and each of the boosting elements being electrically connected in series with the node A and one of the source and the drain of the first MOS transistor;
• means for supplying a first clock signal to a gate of the first MOS transistor;
• means for supplying a second clock signal to a gate of the second MOS transistor, wherein the second clock signal has a reverse polarity to that the first clock signal;
• wherein node A of each boosting element is electrically connected to a first common line, and node B of each boosting element is electrically connected to a second common line, the first common line being electrically separated from a ground potential through a diode and the second common line being electrically separated from ground potential through a diode to effectively operate the second MOS transistor.