Process of fabricating dynamic random access memory cell having inter-level insulating structure without silicon nitride layer between access transistor and storage node

A process of fabricating a semiconductor memory cell, comprising the steps of:

• a) fabricating an access transistor on a semiconductor substrate;
• b) covering said access transistor with a first insulating layer of a first insulating material;
• c) covering said first insulating layer with a second insulating layer of silicon nitride;
• d) forming a contact hole in said first and second insulating layers so as to expose an impurity region of said access transistor thereto;
• e) forming a column portion of a conductive material on said second insulating layer held in contact through said contact hole to said impurity region and covered with a third insulating layer of a second insulating material;
• f) forming a cylindrical portion of said conductive material held in contact with a side surface of said column portion by using a first etchant having a selectivity between said silicon nitride/said second insulating material and said conductive material;
• g) etching said second and third insulating layers by using a second etchant having a selectivity between said first insulating material/said conductive material and said second insulating material/silicon nitride for exposing a top surface of said column portion and a lower surface of said column portion;
• h) covering exposed surfaces of said column portion and exposed surfaces of said cylindrical portion with a dielectric film structure;
• i) covering said dielectric film structure with a cell plate electrode for completing a storage capacitor;
• and
• j) treating said semiconductor memory cell having said access transistor and said storage capacitor with hydrogen for curing crystal defects.