Method for fabricating semiconductor device having CMOS structure
AssigneeNEC Corporation
InventorHitoshi Abiko
Life of this patent
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Abstract
A semiconductor device having a CMOS structure having a low resistivity silicide layer in a source/drain region is fabricated. To realize silicide formation for resistivity reduction of the n-type source/drain region, an impurity-free silicon layer is formed thereon before forming a high melting point metal silicide layer. For the n-type source/drain region, ion implantation is made through the silicon layer. It is thus possible to obtain a shallow junction of the p-type source/drain region, prevent ion implantation time increase and obtain quick fabrication without reducing the ion implantation energy.
Claims15
A method for fabricating a semiconductor device which has a p-type MOS transistor and an n-type MOS transistor and also has a high melting point metal silicide layer formed at least on a source/drain region of each MOS transistor, said method comprising the steps of:
- forming the source/drain region of said n-type MOS transistor through impurity introduction after forming a gate insulating film and a gate electrode of each of the MOS transistors on a silicon substrate;
- forming a silicon layer on each of the source/drain regions of said n- and p-type MOS transistors;
- forming the source/drain region of said p-type MOS transistor through said silicon layer;
- and
- forming said high melting point metal silicide layer by depositing a high melting point metal over an entire surface and causing a reaction of said high melting point metal with said silicon layer.
A method for fabricating a semiconductor device which has a p-type MOS transistor and an n-type MOS transistor and also has a high melting point metal silicide layer formed at least on a source/drain region of each MOS transistor, said method comprising the steps of:
- forming the source/drain regions of at least one of said p-type MOS transistor and said n-type MOS transistor as low impurity concentration regions through impurity introduction after forming a gate insulating film and a gate electrode of each of said MOS transistors on a silicon substrate;
- forming side walls on sides of said gate electrode of each of the MOS transistors;
- forming the source/drain region of said n-type MOS transistor as a high impurity concentration region by ion implantation of an impurity;
- forming a silicon layer by a selective epitaxial growth process on each of the source/drain regions of the n- and p-type MOS transistors;
- forming the source/drain region of said p-type MOS transistor as a high impurity concentration region by ion implantation of a p-type impurity through said silicon layer;
- forming a high melting point metal silicide layer by depositing a high melting point metal over an entire surface and causing a reaction of said high melting point metal with said silicon layer;
- and
- removing the high melting point metal remaining without the silicide reaction.
Dependencies are inferred from the claim text.