Method for manufacturing semiconductor memory device having a stacked capacitor

Abstract

A method for manufacturing a semiconductor memory device comprising the steps of forming a switching transistor including a gate insulating film, a gate electrode, and source and drain regions on a semiconductor substrate; forming a first insulating film on the substrate including the switching transistor; selectively etching the first insulating film to form a contact hole exposing the source or drain region of the switching transistor; forming a second insulating film on the substrate to fill the contact hole; patterning the second insulating film and the first insulating film to a predetermined pattern to thereby form a second insulating film pattern and a first insulating film pattern; selectively removing the first insulating film pattern; forming a conductive layer on an entire surface of the second insulating film pattern; selectively etching the conductive layer by using the second insulating film pattern as a mask, to thereby form a capacitor storage electrode; removing the second insulating film pattern; forming a capacitor dielectric film on an entire surface of the capacitor storage electrode; and forming a capacitor plate electrode on an entire surface of the capacitor dielectric film.

Dependencies are inferred from the claim text.