Process of fabricating semiconductor device having capacitor electrode implanted with boron difluoride
AssigneeNEC Corporation
InventorsSadayuki Ohnishi, Koichi Ando
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Abstract
A stacked storage capacitor of a dynamic random access memory cell has a p-type polysilicon layer forming an upper part of an accumulating electrode, a dielectric film structure and a p-type polysilicon counter electrode, and boron difluoride is ion implanted into a non-doped polysilicon layer for the counter electrode so as to decrease leakage current density rather than a boron-implanted polysilicon counter electrode.
Claims12
A process of fabricating a semiconductor device, comprising the steps of:
- a) forming a first electrode having a first semiconductor layer doped with a p-type impurity;
- b) covering a surface of said first semiconductor layer with a dielectric layer;
- c) covering said dielectric layer with a second semiconductor layer;
- and
- d) implanting boron difluoride into said second semiconductor layer for forming a second electrode held in contact with said dielectric layer, said first electrode, said dielectric layer and said second electrode form in combination a capacitor.
A process of fabricating a dynamic random access memory cell, comprising the steps of:
- preparing a semiconductor substrate;
- fabricating an n-channel enhancement type switching transistor having an n-type source region on said semiconductor substrate;
- covering said n-channel enhancement type switching transistor with an inter-level insulating layer;
- forming a contact hole in said inter-level insulating layer so as to expose a part of said n-type source region to said contact hole;
- plugging said contact hole with a conductive metal piece, said conductive metal piece being held in contact with said n-type source region;
- depositing a first non-doped polysilicon layer over said inter-level insulating layer so as to be held in contact with said conductive metal piece;
- implanting boron difluoride into said first non-doped polysilicon layer so as to convert said first non-doped polysilicon layer to a first p-type polysilicon layer;
- treating said first p-type polysilicon layer with heat;
- patterning said first p-type polysilicon layer into an accumulating electrode;
- depositing a silicon nitride layer over said accumulating electrode,
- oxidizing a surface portion of said silicon nitride layer so as to form a dielectric layer together with a remaining portion of said silicon nitride layer;
- depositing a second non-doped polysilicon layer over said dielectric layer;
- implanting boron difluoride into said second non-doped polysilicon layer so as to convert said second non-doped polysilicon layer into a second p-type polysilicon layer;
- treating said second p-type polysilicon layer with heat;
- and
- patterning said second p-type polysilicon layer into a counter electrode.
A process of fabricating a semiconductor device including a dynamic random access memory cell having a capacitor, comprising the step of ion implanting boron difluoride into a polysilicon over a dielectric layer for forming a counter electrode.
Dependencies are inferred from the claim text.