Signal input unit for semiconductor memory device

Abstract

A signal input unit for a semiconductor memory device comprising a signal input terminal, an electrostatic discharge protection circuit for discharging an electrostatic signal of high level from the input terminal to a ground voltage source, a signal transfer circuit connected in parallel to the electrostatic discharge protection circuit, for switching a normal input signal from the input terminal, a signal transfer control circuit for controlling a switching operation of the signal transfer circuit, and a signal input circuit for buffering an output signal from the electrostatic discharge protection circuit or the signal transfer circuit and transferring the buffered signal to an internal circuit of the semiconductor memory device. The electrostatic discharge protection circuit sufficiently discharges the external electrostatic signal to the ground voltage source in a standby mode of the semiconductor memory device. The signal transfer circuit is connected in parallel to the electrostatic discharge protection circuit so that the normal input signal can be transferred directly to the signal input circuit in an operation mode of the semiconductor memory device with no delay by the electrostatic discharge protection circuit. Therefore, a signal delay can be prevented.

Dependencies are inferred from the claim text.