Protective circuit for semiconductor integrated circuit

A protective circuit for a semiconductor integrated circuit, comprising:

• at least one transistor provided on a substrate;
• a first conducting type region provided on said substrate;
• and
• a second conducting type first diffused part and second diffused part provided in a surface of said region;
• wherein said first diffused part is connected to a ground line for said at least one transistor, and said second diffused part is connected to an external terminal.

A protective circuit for a semiconductor integrated circuit, comprising:

• at least one transistor provided on a substrate;
• a first conducting type first protective device region provided on said substrate;
• a second conducting type first diffused part and second diffused part provided in a surface of said first protective device region;
• a first conducting type second protective device region provided on said substrate;
• and
• a second conducting type third diffused part and fourth diffused part provided in a surface of said second protective device region;
• wherein said first diffused part is connected to a power line of said at least one transistor, and said second diffused part is connected to an external terminal;
• and
• said third diffused part is connected to a ground line of said at least one transistor, and said fourth diffused part is connected to said external terminal.

A protective circuit for a semiconductor integrated circuit, comprising:

• at least one transistor provided on a substrate;
• a first conducting type first protective device region provided on said substrate;
• a second conducting type first diffused part and second diffused part provided in a surface of said first protective device region;
• a first conducting type second protective device region provided on said substrate;
• and
• a second conducting type third diffused part and fourth diffused part provided in a surface of said second protective device region;
• wherein said first diffused part is connected to an input signal line of a pull-up transistor, and said second diffused part is connected to an external terminal;
• and
• said third diffused part is connected to an input signal line of a pull-down transistor, and said fourth diffused part is connected to said external terminal.