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US 5,687,117 AGranted
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry
AssigneeMicron Quantum Devices, Inc.
InventorsChristophe J. Chevallier, Vinod C. Lakhani
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Abstract
A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
Claims42
A flash memory array arrangement comprising:
- a plurality of erase blocks, with each of the erase blocks including flash memory cells, with the memory cells each including
- (a) a source region,
- (b) a drain region spaced apart from the source region so as to define a channel region intermediate the source and drain regions,
- (c) a control gate disposed over the channel region;
- and
- (d) a floating gate positioned intermediate and electrically insulated from the channel region and the control gate;
- with each erase block including a group of the memory cells arranged in an array comprising a plurality of rows and a plurality of columns, with each cell in one of the rows having their control gates connected to a common word line and with each cell in one of the columns having their drain regions connected to a common bit line and with each of the source regions being connected to a common source line;
- control means for reading, programming and erasing cells of the array, with the control means including source line control means for causing the common source line of one of the erase blocks to go to a first state when one of the cells of the erase block associated with the common source line is being read and to a second state when a cell of one of the erase blocks other than the associated erase block is being read and for causing the common source line of one of the erase blocks to go to a third state when one of the cells of the erase block associated with the common source line is being programmed and to a fourth state when a cell of one of the erase blocks other than the associated erase block is being programmed and for causing the common source line of one of the erase blocks to go to a fifth state when the cells of the erase block associated with the common source line are being erased and to a sixth state when one of the erase blocks other than the associated erase block is being erased and wherein at least one of the second, fourth and sixth states is a high impedance state.
5 more elements
An arrangement of flash memory cells comprising:
- first and second erase blocks sharing common bit lines, with each erase block including flash memory cells arranged into an array of rows and columns, with the cells in a column connected to the common bit lines and the cells in a row connected to a common word line and with each erase block including a common source line;
- a source line decoder circuit comprising a separate control transistor associated with each of the common source lines, with the control transistor having an input terminal connected to the associated source line and an output terminal connected to a common global source line and a control terminal for receiving a control signal that causes the transistor to switch between a conductive and non-conductive state.
A flash memory array arrangement comprising:
- a plurality of erase blocks, with each of the erase blocks including flash memory cells, with the memory cells each including a source, a drain and a control gate;
- with each erase block including a group of the memory cells arranged in an array comprising a plurality of rows and a plurality of columns, with each cell in one of the rows having the control gate connected to a common word line and with each cell in one of the columns having the drain connected to a common bit line and with each of the sources being connected to a common source line;
- a memory controller configured to carry out memory operations including reading, programming and erasing the cells of the array, with the memory controller comprising source line control circuitry configured to cause the common source line of one of the erase blocks to go to a first state when one of the cells of the erase block associated with the common source line is being read and to a second state when a cell of one of the erase blocks other than the associated erase block is being read and configured to cause the common source line of one of the erase blocks to go to a third state when one of the cells of the erase block associated with the common source line is being programmed and to a fourth state when a cell of one of the erase blocks other than the associated erase block is being programmed and for causing the common source line of one of the erase blocks to go to a fifth state when the cells of the erase block associated with the common source line are being erased and to a sixth state when one of the erase blocks other than the associated erase block is being erased and wherein at least one of the second, fourth and sixth states is a high impedance state.
An arrangement of flash memory cells comprising:
- first and second erase blocks sharing common bit lines, with each erase block including flash memory cells arranged into an array having a plurality of rows and a plurality of columns, with the cells in a column connected to the common bit lines and the cells in a row connected to a common word line and with each erase block including a common source line;
- a source line decoder circuit comprising a separate control transistor associated with each of the common source lines, with the control transistor being disposed outside the array and having an input terminal connected to the associated source line and an output terminal connected to a common global source line and a control terminal for receiving a control signal that causes the transistor to switch between a conductive and non-conductive state.
A method of controlling the operation of an array arrangement of flash memory cells, with the array arrangement comprising a plurality of erase blocks, with each of the erase blocks comprising an array of the cells, with the cells being arranged into a plurality of rows and columns, with each cell in one of the columns being connected to a common bit line and with each cell in one of the rows being connected to a common word line and with each cell being connected to a common source line, said method comprising the following steps:
- selecting a first one of the erase block on which a memory operation is to be performed, with remaining erase blocks being deselected;
- setting the source line of the selected erase block to a first state and the source line of the deselected erase blocks to a second state in the event the memory operation is a read operation;
- setting the source line of the selected erase block to a third state and the source line of the deselected erase blocks to a fourth state in the event the memory operation is a program operation;
- setting the source line of the selected erase block to a fifth state and the source line of the deselected erase blocks to a sixth state in the event the memory operation is an erase operation, with at least one of the second, fourth and sixth states being a high impedance state;
- and
- completing the memory operation on the selected erase block.
3 more elements
Dependencies are inferred from the claim text.