US 5,686,754 AGranted

Polysilicon field ring structure for power IC

AssigneeInternational Rectifier Corporation

InventorsChongwook Chris Choi, Niraj Ranjan

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Abstract

A polysilicon field ring structure is used to eliminate any type of unwanted surface current leakage in an integrated power chip having high voltage and low voltage areas and enclosed in a plastic housing. All P-type diffusions not biased to the ground potential are surrounded by rings biased to the supply potential, and all N-type diffusions not biased to the supply potential are surrounded by rings biased to the ground potential.

Claims14

Dependent claims

A CMOS integrated circuit chip comprising a silicon substrate of one conductivity type and having at least one high voltage section aid at least one low voltage section;

at least one isolation member for isolating said at least one high voltage section and said at least one low voltage section;
a junction-receiving surface;
a diffusion well of the other conductivity type in said junction-receiving surface;
at least first and second spaced diffusions of said one conductivity type formed into said well and extending from said junction-receiving surface;
at least third and fourth spaced diffusions of said other conductivity type formed in said junction-receiving surface;
said first and second diffusions being included in first and second MOS transistors of said one conductivity type;
said third and fourth diffusions being included in third and fourth MOS transistors of said other conductivity type;
said first, second, third and fourth transistors being connected to define a CMOS circuit having a supply input terminal and a ground potential terminal;
said junction-receiving surface of said substrate having an insulation coating thereon;
source, drain and gate signal lines embedded in said insulation coating;
and a plastic chip housing having inherent contaminant ions therein in contact with said insulation coating;
the improvement which comprises a plurality of polysilicon rings embedded in said insulation coating each of which at least partly surrounds at least one of said first, second, third and fourth diffusions;
said rings being located beneath the source, drain and gate signal lines;
said rings surrounding said first and second diffusions being connected to one of said supply terminal or said ground potential terminal, said one of said supply terminal or said ground potential terminal being said supply terminal when said one conductivity type is P-type and being said ground terminal when said one conductivity type is N-type so that the electrical potential of said rings surrounding said first and second diffusions shield said silicon surface beneath said rings from the electrical potential formed by contaminant ions in said plastic housing thereby preventing inversion of the silicon surface beneath said rings;
said third and fourth diffusions being connected to the other of said supply terminal or said ground potential terminal so that the electrical potential of said rings surrounding said third and fourth diffusions shield said silicon surface beneath said rings from the electrical potential formed by contaminant ions in said plastic housing thereby preventing said inversion of the silicon surface beneath said rings.

12 more elements

An integrated circuit chip suitable for operating at high voltages, said chip comprising:

a silicon substrate of a first conductivity type;
a silicon layer of a second conductivity type having at least one high voltage section and at least one low voltage section, at least one of said at least one high voltage section and at least one of said at least one low voltage section each including at least one diffusion region;
at least one isolation member for isolating the at least one high voltage section and at least one low voltage section;
a passivation layer located on an upper surface of the silicon substrate;
a plastic housing located on an upper surface of the passivation layer to enclose an upper surface of the chip;
a plurality of pin connectors extending through the plastic housing to provide electrical connection to the chip;
at least one polysilicon ring completely surrounding the at least one diffusion region and being connected to a supply potential terminal when said at least one diffusion region is P-type or to a ground potential terminal when said at least one diffusion region is N-type so that the electrical potential of said at least one polysilicon ring shields said silicon surface beneath said at least one polysilicon ring from the electrical potential formed by contaminant ions in said plastic housing thereby preventing surface field leakage caused by said contaminant ions;
and
source, drain and gate signal lines located on the upper surface of the chip, said at least one polysilicon ring being located beneath the source, drain and gate signal lines.

6 more elements

Dependencies are inferred from the claim text.

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Abstract

A CMOS integrated circuit chip comprising a silicon substrate of one conductivity type and having at least one high voltage section aid at least one low voltage section;

at least one isolation member for isolating said at least one high voltage section and said at least one low voltage section;
a junction-receiving surface;
a diffusion well of the other conductivity type in said junction-receiving surface;
at least first and second spaced diffusions of said one conductivity type formed into said well and extending from said junction-receiving surface;
at least third and fourth spaced diffusions of said other conductivity type formed in said junction-receiving surface;
said first and second diffusions being included in first and second MOS transistors of said one conductivity type;
said third and fourth diffusions being included in third and fourth MOS transistors of said other conductivity type;
said first, second, third and fourth transistors being connected to define a CMOS circuit having a supply input terminal and a ground potential terminal;
said junction-receiving surface of said substrate having an insulation coating thereon;
source, drain and gate signal lines embedded in said insulation coating;
and a plastic chip housing having inherent contaminant ions therein in contact with said insulation coating;
the improvement which comprises a plurality of polysilicon rings embedded in said insulation coating each of which at least partly surrounds at least one of said first, second, third and fourth diffusions;
said rings being located beneath the source, drain and gate signal lines;
said rings surrounding said first and second diffusions being connected to one of said supply terminal or said ground potential terminal, said one of said supply terminal or said ground potential terminal being said supply terminal when said one conductivity type is P-type and being said ground terminal when said one conductivity type is N-type so that the electrical potential of said rings surrounding said first and second diffusions shield said silicon surface beneath said rings from the electrical potential formed by contaminant ions in said plastic housing thereby preventing inversion of the silicon surface beneath said rings;
said third and fourth diffusions being connected to the other of said supply terminal or said ground potential terminal so that the electrical potential of said rings surrounding said third and fourth diffusions shield said silicon surface beneath said rings from the electrical potential formed by contaminant ions in said plastic housing thereby preventing said inversion of the silicon surface beneath said rings.

12 more elements