Semiconductor device having a CMOS element as a buffer
AssigneeOki Electric Industry Co., Ltd.
InventorsTamihiro Ishimura, Sampei Miyamoto
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AssigneeOki Electric Industry Co., Ltd.
InventorsTamihiro Ishimura, Sampei Miyamoto
Estimating the term…
A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device as set forth in claim 15, wherein said first MOS transistor and said second MOS transistor respectively comprise a CMOS output buffer for turning on or off in accordance with a voltage level applied to the respective gates and for generating output signals.
A semiconductor device comprising:
Dependencies are inferred from the claim text.