US 5,686,746 AGranted

Semiconductor memory device and a method of making the same

AssigneeNippon Steel Corporation

InventorShoichi Iwasa

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device comprises a field shield element isolation structure defining a plurality of electrically isolated element regions and a plurality of memory cells in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor. A plurality of bit lines extends in a row direction and a plurality of word lines in a column direction. A memory cell pair is formed in each of the element regions and includes two adjacent memory cells disposed in the row direction. Each of the transistors of the two memory cells in each pair has two impurity diffusion layers, one of which is common to both transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film. A second pad is formed on the other impurity diffusion layer of each transistor to extend over a portion of the element isolation structure and adjacent thereto in the column direction. A lower electrode of a capacitor of memory cell in each pair is formed on and insulated from the bit line connected to the common impurity diffusion layer of the respective transistors and to the other impurity diffusion layer through one of the second pad polycrysatalline films.

Claims7

Dependent claims

A semiconductor memory device comprising:

a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another;
a plurality of memory cells disposed in a matrix of rows and columns, each memory cell including a transistor having a gate electrode and two impurity diffusion layers and a capacitor electrically connected to one of said two impurity diffusion layers;
a plurality of bit lines extending in a row direction;
a plurality of word lines extending in a column direction;
a plurality of memory cell pairs, each memory cell pair being formed in one of the plurality of element regions and including adjacent two of the memory cells disposed in the row direction, each of the transitors of the two memory cells constituting the memory cell pair having two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines disposed immediately above the one impurity diffusion layer and extending in the row direction through a first pad polycrystalline silicon film;
a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each of the transitors of the memory cells constituting each memory cell pair and extending over a portion of the element isolation structure defining one of the element regions in which the memory cell pair is formed and adjacent in the column direction to the one element region;
and
a lower electrode of the capacitor of each of the memory cells constituting each memory cell pair formed on and insulated from the one bit line to which the one impurity diffusion layer is connected and connected to the other impurity diffusion layer through the second pad polycrystalline silicon film.

5 more elements

A semiconductor memory device comprising:

a field shield element isolation structure for defining a plurality of element regions electrically isolated from each other;
a plurality of memory cells disposed in a matrix of rows and columns, each of said memory cells including a transistor having two impurity diffusion layers and a gate electrode and a capacitor;
a plurality of bit lines extending in a row direction;
a plurality of word lines extending in a column direction;
a plurality of memory cell pairs, each memory cell pair being formed in one of the plurality of element regions and including adjacent two of the memory cells disposed in the row direction, each of the transistors of the two memory cells constituting the memory cell pair having two impurity diffusion layers, one of said two impurity diffusion layers being common to both the transistors and connected to one of the bit lines disposed immediately above the one impurity diffusion layer and extending in the row direction through a first pad polycrystalline silicon film;
the other of said two diffusion layers being formed at a position deviated in the column direction with respect to said one bit line extending over said one impurity diffusion layer so that said other impurity diffusion layer is positioned immediately below a gap between adjacent two of said bit lines;
and
a lower electrode of the capacitor of each of the memory cells constituting each memory cell pair formed on and insulated from said one bit line to which the one impurity diffusion layer common to the transistors of said memory cell pair is connected and connected to the other impurity diffusion layer of the transitor of the memory cell through a second pad polycrystalline silicon film.

5 more elements

Dependencies are inferred from the claim text.