US 5,686,739 A · Three terminal tunnel device

Abstract

Disclosed is a three terminal tunnel device exhibiting a tunneling of carriers in a forward direction. The device comprises an intrinsic semiconductor region, an n-type degenerate semiconductor source region abutting one side of the intrinsic semiconductor region, a p-type degenerate semiconductor drain region abutting an opposite side of the intrinsic semiconductor region, an insulation region separating the three semiconductor regions from a semiconductor substrate, and a gate electrode being provided over the intrinsic semiconductor region through an insulation layer, whereby voltage signals to be applied to the gate electrode permit controlling a carrier concentration at a surface of the intrinsic semiconductor region. The device permits controlling a tunneling current of a forward-biased degenerate p-n junction and a current-voltage characteristic manifesting a negative differential resistance with the gate voltage signals.

Claims26

Dependent claims

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising:

an isolation region;
an intermediate region made of a non-degenerated semiconductor and provided on said isolation region;
an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region;
a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region;
a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region;
and
a control electrode provided on said insulation layer for applying an electric field to said intermediate region;
wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said non-degenerated semiconductor into a degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic;
and
wherein said isolation region comprises an insulator selected from the group consisting of SiO.sub.2, SiN4, SiON, Al.sub.2 O.sub.3, TiO.sub.2, PbZrTiO.sub.3, and CaF.

7 more elements

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising:

an isolation region;
an intermediate region made of a non-degenerated semiconductor and provided on said isolation region;
an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region;
a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region;
a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region;
and
a control electrode provided on said insulation layer for applying an electric field to said intermediate region;
wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said non-degenerated semiconductor into a degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic;
and
wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

7 more elements

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising:

an isolation region;
an intermediate region made of a degenerated semiconductor and provided on said isolation region;
an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region;
a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region;
a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region;
and
a control electrode provided on said insulation layer for applying an electric field to said intermediate region;
wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic;
and
wherein said isolation region comprises an insulator selected from the group consisting of SiO.sub.2, SiN.sub.4, SiON, Al.sub.2 O.sub.3, TiO.sub.2, PbZrTiO.sub.3, and CaF.

7 more elements

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising:

an isolation region;
an intermediate region made of a degenerated semiconductor and provided on said isolation region;
an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region;
a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region;
a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region;
and
a control electrode provided on said insulation layer for applying an electric field to said intermediate region;
wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic;
and
wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

7 more elements

Dependencies are inferred from the claim text.

Three terminal tunnel device

Life of this patent

Three terminal tunnel device

Life of this patent

Abstract

Claims26