Method of fabricating an electrically alterable resistive component using germanium

A process for fabricating an electrically alterable resistive component in an integrated circuit which includes a semiconductor substrate having a major surface and an insulating layer over said surface;

• said process including the steps of:
• forming a bottom electrical lead on said insulating layer;
• depositing and patterning a layer of electrically alterable material, which changes resistance irreversibly, such that the patterned electrically alterable material overlies and is coupled to said bottom lead;
• forming a top electrical lead which extends over and is there coupled to said electrically alterable material;
• limiting said electrically alterable material to consist of germanium, with or without dopant atoms;
• and,
• confining said electrically alterable material, from its deposition through a predetermined final step that completes said integrated circuit, to temperatures which cause said electrically alterable material to have a smaller crystalline grain size than that of polycrystalline germanium.