US 5,686,336 AGranted

Method of manufacture of four transistor SRAM cell layout

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorJin-Yuan Lee

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Abstract

In accordance with still another aspect of this invention, a set of cross-coupled inverters provide a bistable flip flop formed on a semiconductor substrate with a pair of FOX regions defining an area on the surface of a substrate. The substrate is composed of a semiconductor material with a pair of buried contact regions in the silicon substrate juxtaposed with the FOX regions. A control gate electrode is formed on a gate oxide layer on the surface of the substrate between the pair of the FOX regions. A source region and drain region are formed in the substrate juxtaposed with the control gate electrode to form a parasitic FET device between the FOX regions, the source region and the drain region and reaching to separate ones of the buried contact regions. An interpolysilicon dielectric layer over the control gate electrode covers the device and the power supply conductor passes over the control gate electrode.

Claims16

Dependent claims

A method of fabrication of a Static Random Access Memory (SRAM) silicon device including a plurality of field-effect transistors (FETs) in a form of a set of cross-coupled inverters forming a bistable flip flop formed on a semiconductor substrate, said method comprising

forming a field oxide structure on a surface of a semiconductor substrate,
implanting a pair of local buried contacts into said substrate,
forming a first polysilicon layer on said substrate,
forming a first mask and etching said first polysilicon layer to form a control gate electrode connecting to said set of cross-coupled inverters and interconnection lines to said transistors,
forming spacers adjacent to said control gate electrode and said interconnection lines,
forming source region and drain region in said substrate,
forming a dielectric layer over said SRAM device,
forming a second polysilicon layer on said dielectric layer, and
forming a second mask and etching said second polysilicon layer to form a voltage line over said gate.

6 more elements

Dependencies are inferred from the claim text.