Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel

A method of fabricating a pair of thin film transistors having improved electrical characteristics on a static random access memory cell, comprising the steps of:

• providing a semiconductor substrate having device areas and field oxide areas and further having N-channel field effect transistors (FETs) and word lines formed from a first polysilicon layer and further comprising said pair of thin film transistors formed by;
• depositing a first insulating layer on said substrate;
• depositing a second polysilicon layer on said first insulating layer;
• patterning said second polysilicon layer on said first insulating layer forming a first and second gate electrodes;
• depositing a second insulating layer thereby forming a gate oxide on said first and second gate electrodes;
• depositing an N-type amorphous silicon layer on said second insulating layer;
• annealing said amorphous silicon layer thereby recrystallizing said amorphous silicon layer and thereby forming a third polysilicon layer;
• masking with photoresist portions of said third polysilicon layer over said first and second gate electrodes and ion implanting a P-type conductive dopant elsewhere in said third polysilicon layer;
• patterning said third polysilicon layer leaving N.sup.- doped portions on said first and second gate electrodes and thereby forming a first N.sup.- doped silicon channel region over said first gate electrode and forming a second N.sup.- doped silicon channel region over said second gate electrode, said channels contiguous with P-doped portions of said third polysilicon layer and thereby providing source/drain regions for said first and second N.sup.- doped silicon channel regions;
• said first gate electrode extends over and electrically contacts the drain region of said second N.sup.- doped silicon channel, and said second gate electrode extends over and electrically contacts the drain of said first N.sup.- doped silicon channel, and said source regions of said first and second N.sup.- doped silicon channels extending to and electrically connected to a power supply;
• depositing a conformal third insulating layer on said N.sup.- doped silicon channel regions;
• depositing a metal layer on said third insulating layer;
• photoresist masking and etching said metal layer leaving portions of said metal layer on said third insulating layer and covering completely said thin film transistor P-channels thereby providing metal shielding and further portions of said metal layer forming bit lines for said static random access memory cell;
• exposing said thin film transistor P-channels covered with said metal layer to a hydrogen plasma which reduces the interface traps and improves reliability;
• depositing a fourth insulating layer over said thin film transistor P-channels and thereby passivating and completing said pair of thin film transistors on said static random access memory device.