Method for reduced pitch lithography
AssigneeCypress Semiconductor Corporation
InventorJames M. Cleeves
Life of this patent
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AssigneeCypress Semiconductor Corporation
InventorJames M. Cleeves
Estimating the term…
A lithographic patterning process uses multiple exposures to provide for relatively reduced pitch for features of a single patterned layer. A first imaging layer is exposed to radiation in accordance with a first pattern and developed. The resulting patterned layer is stabilized. A second imaging layer is subsequently formed to surround the first patterned layer, exposed to radiation in accordance with a second pattern, and developed to form a second patterned layer. As the first patterned layer has been stabilized, the first patterned layer remains with the second patterned layer to produce a single patterned layer. For another embodiment, a single imaging layer is patterned by exposure to radiation in accordance with two separate patterns. An exposed portion of the imaging layer is suitably stabilized to withstand subsequent lithographic process steps.
A lithography method for semiconductor fabrication using a semiconductor wafer, comprising the steps of:
A lithography method for semiconductor fabrication using a semiconductor wafer, comprising the steps of:
Dependencies are inferred from the claim text.