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US 5,684,321 AGranted
Semiconductor device having an input protection circuit
AssigneeKabushiki Kaisha Toshiba
InventorJunichi Okamura
Life of this patent
Estimating the term…
Abstract
An input protection circuit is formed on a semiconductor substrate. A resistive element of an impurity diffusion region is electrically isolated from a main region of the substrate by a first double well structure. A bipolar transistor is connected to the resistive element which is electrically isolated from the main region of the substrate by a second double well structure. An input pad is connected to the bipolar transistor.
Claims25
A semiconductor device, comprising:
- a semiconductor substrate of a first conductivity type;
- a first terminal;
- a second terminal;
- a first outer well of a second conductivity type formed in said semiconductor substrate;
- a first inner well of the first conductivity type formed in said first outer well;
- a second outer well of a second conductivity type formed in said semiconductor substrate;
- a second inner well of the first conductivity type formed in said second outer well;
- a resistive element comprising a diffusion region of the second conductivity type formed in said first inner well;
- and
- an input protection circuit element having at least one PN junction formed in said second inner well, wherein said resistive element and said input protection circuit element are connected in series between said first terminal and said second terminal and said resistive element is electrically isolated from said PN junction.
7 more elements
An input protection circuit formed on a semiconductor substrate, comprising:
- a resistive element comprising an impurity diffusion region electrically isolated from a main body of said semiconductor substrate by a first double well arrangement;
- a bipolar transistor connected to said resistive element, said bipolar transistor being electrically isolated from said main body of said semiconductor substrate by a second double well arrangement, wherein said first double well arrangement is independent of said second double well arrangement;
- and p1 an input terminal connected to said bipolar transistor.
An input protection circuit formed on a semiconductor substrate for protecting internal circuits, comprising:
- a first terminal;
- a second terminal;
- at least one PN junction, said PN junction being electrically separated from a main body of said semiconductor substrate;
- and
- a resistive element comprising an impurity diffusion region which is electrically separated from the main body of said semiconductor substrate, wherein said PN junction and said resistive element are connected in series between said first terminal and said second terminal and said resistive element is electrically isolated from said PN junction.
2 more elements
A semiconductor device, comprising:
- a signal input terminal for receiving an externally supplied input signal;
- an input protection circuit connected to said signal input terminal;
- a reference voltage generation circuit for generating a constant reference voltage;
- and
- a comparison circuit connected to said input protection circuit and said reference voltage generation circuit for comparing the input signal and the reference voltage,
- wherein said reference voltage generation circuit and said input protection circuit are electrically isolated by a double well having at least two PN junctions.
3 more elements
A semiconductor device, comprising:
- a first pad;
- a second pad;
- a third pad:
- a first bipolar transistor having a base, a first current terminal connected to said second pad, and a second current terminal connected to said first pad;
- a second bipolar transistor having a base, a first current terminal connected to said second pad, and a second current terminal connected to said third pad;
- a resistive element separated from the first and the second bipolar transistors and electrically isolated from the current terminals of said first and second bipolar transistors by a double well structure, said resistive element having a first terminal connected to the bases of said first and second bipolar transistors and a second terminal connected to said third pad.
3 more elements
A semiconductor device comprising:
- a first pad;
- a second pad;
- a third pad:
- a first bipolar transistor having a base connected to said third pad, a first current terminal, and a second current terminal connected to said first pad;
- a second bipolar transistor having a base connected to said third pad, a first current terminal, and a second current terminal connected to said third pad;
- a resistive element separated from said first and second bipolar transistors and electrically isolated from the current terminals of said first and second bipolar transistors by a double well structure, said resistive element having a first terminal connected to the first current terminals of said first and second bipolar transistors and a second terminal connected to said second pad.
3 more elements
A semiconductor device, comprising:
- a plurality of pads arranged linearly;
- a plurality of input protection elements arranged linearly alongside said pads;
- a signal bus arranged along side said input protection elements;
- and
- a resistive element connected to and shared by each of said plurality of input protection elements.
2 more elements
A semiconductor device, comprising:
- first, second, third, and fourth rectangular core blocks each having a plurality of memory cells arranged in matrix;
- a first buffer block arranged between said first and second rectangular core blocks, said first buffer block having a plurality of address pads and first input protection circuits arranged linearly;
- and
- a second buffer block arranged between said third and fourth rectangular core blocks, said second buffer block having a plurality of data I/O pads and second input protection circuits arranged linearly, wherein
- said first buffer block includes a first resistive element electrically isolated from said first, second, third, and fourth core blocks by a first double well;
- and
- said second buffer block includes a second resistive element electrically isolated from the first, second, third, and fourth core blocks by a second double well.
4 more elements
Dependencies are inferred from the claim text.