Semiconductor device having transistor pair

A semiconductor memory device comprising a memory element comprising:

• a first thin film semiconductor layer having a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;
• a second thin film semiconductor layer having a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;
• said first and second layers are laminated one atop the other;
• an element for reading which is located in a facing relation to said channel region of one of said first and said second thin film semiconductor layers;
• and
• a third thin film semiconductor layer which is disposed between said one of said first and second thin film semiconductor layers and said element for reading, said third thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween.

A semiconductor memory device comprising a memory element comprising:

• a first thin film semiconductor layer having a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;
• a second thin film semiconductor layer having a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;
• said first and second layers are laminated one atop the other;
• a gate for writing which is located in a facing relation to said channel region of one of said thin film semiconductor layers;
• an element for reading which is located in a faced relation to said channel region of the other one of said thin film semiconductor layers;
• a third thin film semiconductor layer between said one of said first and second thin film semiconductor layers and said gate for writing, said third thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type a channel region sandwiched therebetween;
• and
• a fourth thin film semiconductor layer which is disposed between the other one of said first and second thin film semiconductor layers and said element for reading, said fourth thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween.

A semiconductor memory device, comprising:

• at least four thin film semiconductor layers, each including a semiconductor region of a first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween, said layers are laminated one atop the other into a lamination with insulator layers interposed therebetween with said semiconductor regions of the same conductivity type facing each other;
• a gate for writing disposed in an opposing relation to said channel region of one of said thin film semiconductor layers which forms a first end of said lamination with an insulator layer interposed between said gate for writing and said thin film semiconductor layer forming the first end of said lamination;
• and
• an element for reading disposed in an opposing relation to said channel region of one of said thin film semiconductor layers which forms a second end of said lamination with an insulator layer interposed between said element for reading and said thin film semiconductor layer forming the second end of said lamination.