US 5,684,319 A · Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same

Abstract

A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates. A P+ body contact implantation is performed, thereby forming body contact regions. A final annealing step causes vertical and lateral out-diffusion of the N type dopant from the N+ spacers down into substrate to form source N+ regions which partially underlie the gate polysilicon. A third mask is used to etch a gate contact area on a segment of the polysilicon above the field oxide. Metal is deposited, and a fourth photoresist mask delineates a gate pad region and a source pad region which also extends over the source contacts. A passivation layer is deposited and etched in the source and gate pad regions using a fifth mask. In another embodiment, a trench DMOS transistor is fabricated using an additional mask to guide a dry etch to "dig" the trenches.

Claims43

Dependent claims

A method of fabricating a semiconductor device, the method comprising the steps of:

(a) growing a gate oxide layer of silicon dioxide on an underlying epitaxial layer of a first conductivity type;
(b) depositing a gate conductive layer onto the gate oxide layer;
(c) doping the gate conductive layer with impurities of a first conductivity type;
(d) defining a gate mask over the gate conductive layer;
(e) etching the gate conductive layer and underlying gate oxide layer through the gate mask to form transistor gates;
(f) stripping the gate mask;
(g) growing an insulating oxide layer of silicon dioxide;
(h) implanting impurities of a second conductivity type to form body implant regions in the epitaxial layer;
(i) performing a thermal drive-in to diffuse the impurities of the second conductivity type vertically and laterally to form diffused body regions;
(j) etching the insulating oxide layer so as to remove the insulating oxide layer from regions directly overlying the epitaxial layer while leaving insulating oxide sidewalls that cross-sectionally surround the transistor gates;
(k) depositing polysilicon to form a spacer polysilicon layer;
(l) doping the spacer polysilicon layer with impurities of the first conductivity type;
(m) etching the spacer polysilicon layer to form polysilicon spacers adjacent to the insulating oxide sidewalls;
(n) implanting impurities of the second conductivity type to form body contact implant regions in the epitaxial layer;
and
(o) annealing to diffuse the impurities of the first conductivity type from the spacers into the epitaxial layer to form source regions.

13 more elements

A device structure, comprising:

a first conductive gate of a first conductivity type that is cross-sectionally surrounded by first insulating silicon dioxide and is formed above an epitaxial layer of the first conductivity type;
a first polysilicon spacer of the first conductivity type adjacent to a sidewall of the first insulating silicon dioxide surrounding the first conductive gate and overlying the epitaxial layer;
a first source region of the first conductivity type vertically adjacent to and underlying the first polysilicon spacer, formed within the epitaxial layer, wherein the first source region has a first channel boundary surface portion underlying the first conductive gate and adjacent to the first insulating silicon dioxide, and has a first source contact surface portion extending beyond a furthest horizontal first spacer surface extension so as to allow a metal source contact to overly the first source contact surface portion;
and
a first body region of a second conductivity type formed within the epitaxial layer and containing the first source region, wherein the first body region has a first channel region surface which underlies the first conductive gate and is adjacent to the first insulating silicon dioxide, and has a first highly-doped body contact surface portion extending beyond the first source contact surface portion so as to allow the metal source contact to overly the first body contact surface portion.

2 more elements

A trench DMOS transistor structure, comprising:

a first trench formed in a layer of epitaxial silicon having a first conductivity type;
a first conductive gate in the first trench that is cross-sectionally surrounded by first insulating silicon dioxide and that vertically protrudes above the epitaxial silicon;
a first polysilicon spacer of the first conductivity type adjacent to a sidewall of the first insulating silicon dioxide surrounding the first conductive gate and overlying the epitaxial layer;
a first source region of the first conductivity type vertically adjacent to and underlying the first polysilicon spacer, formed within the epitaxial layer, wherein the first source region has a first vertical channel boundary surface portion beside the first conductive gate and adjacent to the first insulating silicon dioxide, and has a first source contact surface portion extending beyond a furthest horizontal first spacer surface extension so as to allow a metal source contact to overly the first source contact surface portion;
and
a first body region of a second conductivity type formed within the epitaxial layer and containing the first source region, wherein the first body region has a first channel region surface beside the first conductive gate and adjacent to the first insulating silicon dioxide, and has a first highly-doped body contact surface portion extending beyond the first source contact surface portion so as to allow the metal source contact to overly the first body contact surface portion.

3 more elements

Dependencies are inferred from the claim text.

Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same

Life of this patent

Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same

Life of this patent

Abstract

Claims43