Trench capacitor precharge structure and leakage shield
OwnerDonald M. Kenneyinventor
Life of this patent
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Abstract
An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage current shield for the DRAM storage node diffusion, thereby improving the data hold time. A graded impurity region around the storage node diffusion enhances the leakage shielding effect. The structure can be operated independently as a DRAM leakage shield if the precharge circuit is not needed. In that case, a junction diffusion in the structure can be eliminated and a leakage shielding effect is still achieved.
Claims20
A memory array of dynamic random access memory cells formed on a semiconductor substrate, each said cell including a bit line junction, a storage node junction, a first transistor channel region disposed between said bit line junction and said storage node junction, a portion of a first word line gating said first transistor channel region, and a storage capacitor trench disposed adjacent said storage node junction, the improvement comprising:
- a. a third junction disposed adjacent said storage capacitor trench and physically spaced apart from said bit line and said storage node junctions, and
- b. a second word line substantially parallel and coplanar to said first word line and disposed so as to gate a second transistor channel region disposed between the storage node junction and said third junction.
A memory array of dynamic random access memory cells formed on a semiconductor substrate, each said cell including a bit line junction, a storage node junction, a first transistor channel region disposed between said bit line junction and said storage node junction, a portion of a first word line gating said first transistor channel region, and a storage capacitor trench disposed adjacent said storage node junction, the improvement comprising:
- a. a first doped region having a first doping concentration disposed entirely around said storage node junction within said semiconductor substrate, and
- b. a second doped region having a second doping concentration disposed adjacent said first doped region and said bit line junction, and
- c. a second word line substantially parallel and coplanar to said first word line, and disposed so as to at least partially gate a surface extending between the storage node junction and a third junction.
An array of memory cells formed on a semiconductor substrate, each said cell including a first junction utilized as a storage node junction, a second junction utilized as a bit line junction, a first transistor channel region disposed between said first junction and said second junction, a portion of a first word line gating said first transistor channel region, and a storage capacitor trench, the improvement comprising:
- a. a third junction disposed apart from said first and second junctions, and
- b. a second word line substantially parallel and coplanar to said first word line and disposed so as to gate a second transistor channel region disposed between the first junction and said third junction.
Dependencies are inferred from the claim text.