Manufacturing method for ROM array with minimal band-to-band tunneling
AssigneesWaferScale Integration, Inc., American Microsystems, Inc.
InventorsRustom F. Irani, Reza Kazerounian, Mark Michael Nelson
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AssigneesWaferScale Integration, Inc., American Microsystems, Inc.
InventorsRustom F. Irani, Reza Kazerounian, Mark Michael Nelson
Estimating the term…
A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.
A method of manufacturing a read only memory (ROM) array with minimal band-to-band tunneling, the ROM array comprising a core area and a periphery area, the corn area having turned on and turned off core transistors and the periphery area having periphery transistors, the method comprising the steps of:
A method according to claim l and wherein said thickness layer is ROM oxide layer is dictated by the dosage level of said ROM implant which, in turn, is dictated by the maximal desired band-to-band tunneling current.
A method of manufacturing a read only memory (ROM) array with minimal band-to-band tunneling, the ROM array comprising a core area and a periphery area, the core area having turned on and turned off core transistors and the periphery area having periphery transistors, the method comprising the steps of:
A method of manufacturing a read only memory (ROM) array with minimal band-to-band tunneling, the ROM array comprising a core area and a periphery area, the core area having turned on and turned off core transistors and the periphery area having periphery transistors, the method comprising the steps of:
Dependencies are inferred from the claim text.