Method of designing semiconductor integrated circuit apparatus having no dead space

A method of designing a semiconductor integrated circuit apparatus comprising:

• a placement step of generating row information indicating a transistor row in which transistors required for the configuration of a transistor row to be designed so that wiring length is as short as possible, on the basis of net description information of transistors, size information of various transistors constituting net, and ideal module size information which provides constraint relating to size in the X-direction and in Y-direction perpendicular to the X-direction of the transistor row in which the various transistors are placed in the X-direction;
• a row size determination step of generating row size information indicating sizes in the X-direction and Y-direction of the transistor rows;
• each row size determination step of generating, on the basis of the row sizes information, row size indicating size in the X-direction and sizes in the Y-direction of the transistor rows that the rows information indicates;
• and
• a parallel arrangement step of carrying out parallel arrangement of transistors constituting the transistor row so that the transistor row that the row information indicates falls within sizes in the X-direction and Y-direction that the row size information indicates.