US 5,675,161 A · Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications

Abstract

Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area. By separating the portion of the gate on the side wall from that over the surface, along a continuous channel between the source and drain, independently operating storage region and a select/accelerating region are formed along the same channel. This structure allows independent voltages to be applied to the storage gate and the accelerating gate. These CATE cells allow low supply current operation. Since all the operations are low current operations, efficient pumps can be used on chip to provide the required high voltages where needed.

Claims11

Dependent claims

A memory cell, capable of being programmed by using channel accelerated carrier tunneling method of programming, and erase by tunneling, having

a select/accelerating region, along a sidewall of a trench, etched into a surface of a semiconducting layer,
a memory region, adjacent the sidewall of the trench, on the surface of the semiconducting layer,
a step having an edge formed at an intersection of the sidewall of the trench with the surface of the semiconducting layer,
a drain on the surface of the semiconductor material, spaced away from the trench, adjacent the memory region,
a source at a bottom of the trench,
an integrated channel formed by the select/accelerating region and the memory region between the source and the drain,
a carrier discontinuity, in the channel, formed at the edge of the step,
a first conductive gate material, overlaying the select/accelerating region but separated from it by a gate dielectric, which allow independent control of the select/accelerating region of the integrated channel by application of a voltage to the first conductive layer,
a memory element, comprising a floating gate electrode overlaying the memory region but separated from it by a tunnel dielectric, and a control gate overlaying the floating gate electrode but separated from it by an interlayer dielectric, which allow independent control of the memory region by potential on the floating gate electrode, due to charge stored in the floating gate electrode and coupled down voltage from the control gate.

6 more elements

A memory cell capable of being programmed, by carriers in a channel of a MOS device directly, using Channel Accelerated Carrier Tunneling method of programming, comprising,

a semiconducting layer, doped by an impurity of a first conductivity type
a trench etched into a surface of the semiconducting layer,
a step having an edge along an intersection of the surface of the semiconducting and a sidewall of the trench,
a gate dielectric deposed on the side wall of the trench and bottom of the trench, isolating the trench from the semiconducting layer,
an impurity, of a second conductivity type, forming a source of the MOS device, introduced into the bottom of the trench,
a first conductive gate material filling the trench,
an insulating dielectric layer overlaying the trench,
a tunnel dielectric layer deposed on the surface of the semiconducting layer adjacent the step,
a second conductive layer deposed over the tunnel dielectric layer, forming a floating gate electrode,
an interlayer dielectric deposed over the floating gate electrode,
a third conductive layer, forming a control gate, overlaying the interlayer dielectric,
an impurity of the second conductivity type, forming a drain of the MOS device, introduced into the semiconducting layer surface, spaced away from the side wall of the trench, adjacent the floating gate electrode,
memory element formed of the floating gate electrode, the interlayer dielectric and the control gate,
an integrated channel of the MOS device, formed between the source and the drain, having
a first independently controllable select accelerating region, under the gate dielectric, along the side wall of the trench, controlled by a voltage applied to the first conductive layer and
a second independently controller memory region, on the surface of the semiconducting material, under the tunnel dielectric separating the memory element from the semiconducting layer, controlled by charge on the floating gate combined with potential applied to it by coupling down from the control gate,
a carrier discontinuity in the channel at edge of the step, towards which carriers in the select accelerating region are directed, to achieve channel accelerated tunneling during programming.

14 more elements

Dependencies are inferred from the claim text.

Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications

Life of this patent

Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications

Life of this patent

Abstract

Claims11