High speed mis-type intergrated circuit with self-regulated back bias

A method of operating a semiconductor apparatus having a substrate portion, a gate, a source, and a drain, comprising the steps of:

• generating a constant voltage;
• and
• applying said constant voltage to the substrate portion of a MIS transistor via a path having a high resistance value.

A method of operating a semiconductor apparatus comprising, a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias terminal for receiving a constant back bias to be applied to the substrate portion of said MIS transistor, and a resistor, and a resistor having a high value of resistance interposed between the substrate portion of said MIS transistor and the back-bias terminal, said method comprising the steps of:

• estimating a value of a substrate current based on a potential of the substrate portion;
• and
• judging whether said MIS transistor is in an active mode or a standby mode.

A method of manufacturing a semiconductor apparatus having a highly resistive layer formed in a region where a length is smaller than a distance between a source and drain of a first-type MIS transistor comprising at least the steps of:

• forming a resist mask having a pattern obtained by reversing the pattern of the mask for forming a gate electrode of said first-type MIS transistor in an offset position;
• and
• performing ion implantation from a tilted position above said resist mask so as to cause crystal defects in the insulating film.