Three stage ESD protection device

An MOS electrostatic discharge, ESD, protection circuit for protecting a semiconductor device from ESD damage, said ESD protection circuit formed on a doped silicon semiconductor substrate comprising:

• said device including a silicon dioxide gate oxide layer formed on said semiconductor substrate with a thickness between 40.ANG. and 200 .ANG.,
• an input line, an output line, a first node, a second node and a third node, and ground connections,
• first and second resistors each having a proximal end and a distal end,
• said first node connected to:
• said input line, and
• said proximal end of said first resistor,
• said second node connected to:
• said proximal end of said second resistor,
• and
• said distal end of said first resistor,
• said third node connected to:
• said distal end of said second resistor, and
• said output line,
• said first stage including a first MOS transistor and a grounded region formed in said substrate,
• said first MOS transistor including a first source region and a first drain region formed in said substrate, and a control gate electrode therebetween,
• said first drain region being coupled to said first node,
• said control gate electrode and said first source region being connected to said grounded region,
• said second stage including a string of MOSFET transistors connected in a series string with the drain and the control gate of the first of said string connected to the distal end of said first resistor,
• said third stage including a third stage MOSFET device with a control gate connected to the output of said second stage and a source and drain circuit thereof connected between said third node and a said ground connection,
• said gate electrodes being formed of polysilicon with a thickness between 1,000.ANG. and 5,000 .ANG.,
• said source/drain regions having been ion implanted with a dose between 1E15 ions/cm.sup.2 and 7E15 ions/cm.sup.2,
• whereby said transistors dissipate power during an excess energy event.

An MOS electrostatic discharge, ESD, protection circuit for protecting a semiconductor device from ESD damage, said ESD protection circuit formed on a doped silicon semiconductor substrate comprising:

• a first stage including a first field effect transistor formed on said substrate, including a first electrode, a second electrode, and a control element,
• an output stage including an output field effect transistor formed on said substrate, including a drain electrode, a source electrode, and a gate electrode,
• said second electrode and said control element being connected together and grounded to said substrate,
• said first electrode connected to a first end of a first resistor having its second end connected to a second stage including a chain of a plurality of series connected field effect transistors, having a gate and a first electrode connected together, with the first electrode of the first transistor in said chain connected to said resistor and the second electrode of each transistor in said chain connected to the first electrode and the control element of the succeeding transistor in said chain, the control element of the final transistor in said chain connected to said gate electrode of said output stage,
• a second resistor having its first end connected to said second end of said first resistor, said second resistor having a second end,
• said drain electrode of said third stage connected to said second end of said second resistor and said source electrode of said third stage grounded to said substrate.