Method of fabricating DRAM cell with self-aligned contact

A method of fabricating a dynamic random access memory (DRAM) structure in a semiconductor substrate having a first conductivity type, the DRAM structure including source and drain regions of a second conductivity type that is opposite to the first conductivity type formed in the semiconductor substrate in spaced-apart relationship to define a channel region therebetween, a layer of gate dielectric material formed on a surface of the semiconductor substrate above the channel region and extending to at least partially overlap the source region and the drain region, and a conductive gate formed on the layer of gate dielectric material over the channel region, the method comprising:

• forming a layer of first dielectric material on the conductive gate to define, in combination with the conductive gate, a stacked gate structure;
• forming a dielectric sidewall spacer structure on sidewalls of the stacked gate structure and such that at least a first portion of the sidewall spacer structure is formed on gate dielectric materials that overlaps the drain region and at least a second portion of the sidewall spacer structure is formed on gate dielectric material that overlaps the source region;
• forming a layer of second dielectric material over the first dielectric material and extending over the drain region such that the second dielectric material is separated from the drain region by gate dielectric material and the first portion of the sidewall spacer structure, and extending over the source region such that the second dielectric material is separated from the source region by gate dielectric material and the second portion of the sidewall spacer structure;
• forming a contact trench in the second dielectric material, the contact trench having a first edge that is at least partially aligned over the conductive gate and is at least partially defined by the second portion of the sidewall spacer structure, and a second edge that is aligned over the source region, the contact trench defining an exposed surface of the source region;
• forming a conductive lower capacitor plate at least partially over the second dielectric material and to conformally cover the first and second edges of the contact trench and the exposed surface of the source region by forming a first layer of conductive material having a first thickness on the first and second edges of the contact trench and then forming a second layer of conductive material having a second thickness that is less than the first thickness on the first layer;
• forming a layer of capacitor dielectric material over the lower capacitor plate;
• and
• forming a conductive upper capacitor plate over the capacitor dielectric material.