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US 5,672,532 AGranted
Method of forming bit lines having lower conductivity in their respective edges
AssigneeUnited Microelectronics Corp.
InventorsChen Chiu Hsue, Gary Hong
Life of this patent
Estimating the term…
Abstract
A buried bit line ROM is disclosed having orthogonal sets of buried bit lines and polysilicon word lines. Polysilicon spacers are disposed on either side of each of the bit lines. The polysilicon spacers are slightly doped. The bit lines have a doping profile so that the edges of each bit line is doped less and the center of each bit line is doped more.
Claims19
A method for producing a buried bit line ROM cell comprising:
- (a) forming at least one layer on a semiconducting substrate and forming at least two trenches in said at least one layer,
- (b) depositing first and second doped polysilicon spacers on the sidewalls of said trenches,
- (c) forming first and second buried bit lines in said semiconducting substrate through said spacers, wherein said first and second bit lines have a first conductivity type and said semiconducting substrate has a second conductivity type, so that said bit lines have a doping profile such that the conductivity of the bit lines is less at the edges of said bit lines and more at the center of said bit lines,
- (d) forming an oxide layer over said spacers, bit lines and semiconducting substrate, and
- (e) depositing a word line over said oxide layer and oriented orthogonally to said bit lines.
2 more elements
A process for producing a buried bit line ROM cell comprising:
- (a1) depositing a first oxide layer on a semiconducting substrate;
- (a2) depositing a nitride layer on said first oxide layer;
- (a3) masking said nitride layer;
- (a4) etching said nitride layer through said mask to form said trenches in said nitride layer;
- (b) depositing first and second doped poly silicon spacers on the sidewalls of said trenches;
- (c) forming first and second buried bit lines in said semiconducting substrate through said spacers, wherein said first and second bit lines have a first conductivity type and said semiconducting substrate has a second conductivity type, so that said bit lines have a doping profile such that the conductivity of the bit lines is less at the edges of said bit lines and more at the center of said bit lines;
- (d) forming an oxide layer over said spacers, bit lines and semiconducting substrate;
- (e1) removing said nitride layer and said first oxide layer;
- (e2) depositing a polysilicon layer over said oxide layer to form said word line;
- (f) masking and patterning said polysilicon layer for ROM code masking;
- and
- (g) implanting ROM code between said spacers and said buried bit lines.
9 more elements
A method for producing a buried bit line ROM cell comprising:
- (a) forming at least one insulation layer on a semiconducting substrate and forming at least two trenches in said at least one insulation layer,
- (b) depositing first and second doped polysilicon spacers on the sidewalls of said trenches,
- (c) forming first and second buried bit lines in a substrate through said spacers, wherein said first and second bit lines have a first conductivity type and said semiconducting substrate has a second conductivity type, so that said bit lines have a doping profile such that the conductivity of the bit lines is less at the edges of said bit lines and more at the center of said bit lines,
- (d) forming an oxide layer over said spacers, bit lines and semiconducting substrate, and
- (e) depositing a word line over said oxide layer and oriented orthogonally to said bit lines.
2 more elements
Dependencies are inferred from the claim text.