US 5,671,397 A · Sea-of-cells array of transistors

Abstract

The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Claims1

Dependent claims

In a method of constructing a logic inverter which comprises an n-channel and a p-channel field-effect transistor, the improvement comprising:

etching a gate and a conductor connecting drains of the two transistors from a same layer of polysilicon.

Dependencies are inferred from the claim text.

Facts

Application

08/455,503Filed 31 May 1995 · division

Priority

27 Dec 1993

Granted

23 Sep 1997

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10D 84/907
Comprising field effect technology: cMOS gate arrays
Y10S 257/909
Active solid-state devices, e.g. transistors, solid-state diodes: macrocell arrays, e.g. gate arrays with variable size or configuration of cells
H10D
Inorganic electric semiconductor devices

Sea-of-cells array of transistors

Life of this patent

Abstract

Claims1

Sea-of-cells array of transistors

Life of this patent

Abstract

Claims1